In this paper, we present a low-noise, high-gain readout hardware to be used in conjunction with (sub)mm-wave zero bias detectors, to enable high sensitivity (i.e., ∼-50dBm) and fast (i.e., below a second at -50 dBm) power detection.
The developed hardware employs a casc
...
In this paper, we present a low-noise, high-gain readout hardware to be used in conjunction with (sub)mm-wave zero bias detectors, to enable high sensitivity (i.e., ∼-50dBm) and fast (i.e., below a second at -50 dBm) power detection.
The developed hardware employs a cascade of two (COTS) programmable gain amplifier (PGA), capable of reaching up to 90 dB gain (volt to volt), each providing an input referred noise level of 16 nV/√Hz. The signal is then digitized on the same board via a 500 kHz 12bit ADC, providing an SNR of 74 dB. The digitized signal is then readout via an ST microcontroller and transferred to the operator PC via a USB interface. The sensitive bias voltages for the PGAs are provided via the microcontroller, or alternatively can be fed by an external lab grade supply to further improve on the (already high) supply noise rejection from the first stage PGA. The proposed hardware is designed to interface with VDI zero bias detectors, high responsivity and low NEP diodes (around 2000 V/W and below 12 pW/√Hz, respectively) operating in monomodal waveguide bands up to 500 GHz. In this contribution we demonstrate the usage of the developed hardware with WR10, WR6.5, WR5 and WR 3 ZBD diodes.@en
