Powering of medical implants by inductive coupling is an effective technique, which avoids the use of bulky implanted batteries or transcutaneous wires. On the external unit side, class-D and class-E power amplifiers (PAs) are conventionally used, thanks to their high efficiency at high frequencies. The initial specifications driving this study require the use of multiple independent stimulators, which imposes serious constraints on the area and functionality of the external unit. An integrated circuit class-D PA has been designed to provide both small area and enhanced functionality, the latter achieved by the addition of an on-chip (PLL) a dead-time generator and a phase detector. The PA was designed in a 0.18-μm CMOS high-voltage process technology and occupies an area of 9.86 mm². It works at frequencies up to 14 MHz and 30-V supply and efficiencies higher than 80% are obtained at 14 MHz. The PA is intended for a closed-loop transmitter system that optimizes power delivery to medical implants.

This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

Inductive powering for implanted medical devices is a commonly employed technique, that allows for implants to avoid more dangerous methods such as the use of transcutaneous wires or implanted batteries. However, wireless powering in this way also comes with a number of difficulties and conflicting requirements, which are often met by using designs based on compromise. In particular, one aspect common to most inductive power links is that they are driven with a fixed frequency, which may not be optimal depending on factors such as coupling and load. In this paper, a method is proposed in which an inductive power link is driven by a frequency that is maintained at an optimum value f_opt , to ensure that the link is in resonance. In order to maintain this resonance, a phase tracking technique is employed at the primary side of the link; this allows for compensation of changes in coil separation and load. The technique is shown to provide significant improvements in maintained secondary voltage and efficiency for a range of loads when the link is overcoupled.

We are developing an electrode array for epidural spinal cord stimulation and a thin integrated circuit (IC) is to be embedded in it. This paper focuses on the development and characterization of a manual process for thinning individual IC die and discusses the issues associated with thinning small dice by a manual process. The procedure allows easy and controlled post-separation thinning of small (about 1 mm²) silicon chips by grinding. A systematic approach was followed to characterize the technique and repeatability of the results. With the setup we introduced we were able to control the final thickness of the IC with a standard deviation of 9.2 μm. Although no chemical processing is used, a small grit size film can create smooth surfaces, with roughness comparable to reported values after etching, acting as the so-called 'stress-relief' step. Electrical tests performed on a thinned stimulator output stage IC indicated that no die damage was caused by the procedure. Some issues regarding the integration of thinned ICs on flexible substrates and the reliability of gold ball rivet bonds on the ICs' aluminium pads are also discussed.

Inductive powering is an efficient method to wire-lessly transfer power to an implant. On the transmitter side, a power amplifier (class-D or class-E) is used to convert DC power, from a supply unit, into AC power, which can be transferred across the inductive link. At frequencies conventionally used for powering implants, the efficiency of a Class-D power amplifier is highly dependent on the dead time between the switching of the low-side and the high-side switches. Closed-loop techniques can then be adopted to automatically set the appropriate dead time. This paper addresses this issue by presenting the conceptual design of an analog CMOS closed-loop automatic efficiency optimization circuit for class-D PAs, consisting of an analog power meter and a 13-bit programmable delay line. The circuits have been designed in a 0.18μm CMOS technology and simulated using Cadence Spectre.

This paper discusses the design of an application-specific integrated circuit (ASIC) suitable for mounting on a multi-electrode array for epidural spinal cord stimulation in rats. The ASIC acts as a demultiplexer, driving 12 electrodes on the array in any configuration. It is capable of routing biphasic constant current pulses of up to 1 mA to high impedance loads (with a maximum output voltage swing of approximately 25 V) and is small enough to be implanted into a rat's spinal column. Communication with its driver is achieved via 3 wires to minimize the number of interconnections. The circuit was implemented in a 0.18-μm high-voltage CMOS technology occupying a core area of 0.36 mm ². Power dissipation is about 110 μW. Post-layout simulations are presented which show the correct operation of the system.

The design of a very small low-power IC driving 16 electrodes in any combination, for testing different epidural stimulation patterns in freely moving rats using a two wire interface is presented. A scheme is proposed, to receive power, data, clocking information and stimulus current pulses from an external source via the two wires. This is achieved by a combination of time multiplexing and pulse width modulation. The architecture of the system is discussed and simulated results of some building blocks are presented.

A significant problem with clinical deep brain stimulation (DBS) is the high variability of its efficacy and the frequency of side effects, related to the spreading of current beyond the anatomical target area. This is the result of the lack of control that current DBS systems offer on the shaping of the electric potential distribution around the electrode. This paper presents a stimulator ASIC with a tripolar current-steering output stage, aiming at achieving more selectivity and field shaping than current DBS systems. The ASIC was fabricated in a 0.35-μm CMOS technology occupying a core area of 0.71 mm ². It consists of three current sourcing/sinking channels. It is capable of generating square and exponential-decay biphasic current pulses with five different time constants up to 28 ms and delivering up to 1.85 mA of cathodic current, in steps of 4 μA, from a 12 V power supply. Field shaping was validated by mapping the potential distribution when injecting current pulses through a multicontact DBS electrode in saline.