Wireless biosensors are playing a pivotal role in health monitoring, disease detection and management. The development of wireless biosensor nodes and networks strongly relies on the design of novel low-power, low-cost and flexible CMOS sensor readouts. This brief presents a CMOS potentiostat that integrates a control amplifier, a dual-slope ADC and a wireless unit on the same chip. It implements a novel time-based readout scheme, whereby the counter of the dual-slope ADC is moved to the receiver and the sensor current is encoded in the timing between two wireless pulses transmitted via pulse-harmonic modulation across an inductive link. Measured results show that the potentiostat chip can resolve a minimum input current of 10pA at a sampling frequency of 125 Hz and a power consumption of 12 μW .

@en

Point-of-care systems for the detection of infectious diseases are in great demand especially in developing countries. Lateral flow immunoassays are considered ideal biosensors for point-of-care diagnostics due to their numerous advantages. However, to quantify their results a low power, robust electronic reader is needed. A low power CMOS image sensor is presented that can be used in quantitative lateral flow immunoassay readers. It uses a single low power processing capacitive transimpedance amplifier architecture which includes noise cancellation. A chip containing 4 × 64 pixels was fabricated in CMOS 0.35-μm technology. With uniform illumination at 525 nm and 67 frames per second the chip has 1.9 mVrms total output referred noise and a total power consumption of 21 μW. In tests with lateral flow immunoassays the chip detected concentrations of influenza A nucleoprotein from 0.5 ng/mL to 200 ng/mL.

@en

A novel pixel architecture for CMOS image sensors is presented. It uses only one amplifier for both integration of the photocurrent and in-pixel noise cancelation, thus minimizing power consumption. The circuit is specifically designed to be used in readout systems for lateral flow immunoassays. In addition a switching technique is introduced enabling the use of column correlated double sampling technique in capacitive transimpedance amplifier pixel architectures without the use of any memory cells. As a result the reset noise which is crucial in these architectures can be suppressed. The circuit has been designed in a 0.35-μm CMOS technology and simulations are presented to show its performance.@en