This paper presents a low power monolithically integrated optical transmitter with avalanche mode light emitting diodes in a 140 nm silicon-on-insulator CMOS technology. Avalanche mode LEDs in silicon exhibit wide-spectrum electroluminescence (400 nm < λ < 850 nm), which has a significant overlap with the responsivity of silicon photodiodes. This enables monolithic CMOS integration of optocouplers, for e.g. smart power applications requiring high data rate communication with a large galvanic isolation. To ensure a certain minimum number of photons per data pulse (or per bit), light emitting diode drivers must be robust against process, operating conditions and temperature variations of the light emitting diode. Combined with the avalanche mode light emitting diode’s steep current-voltage curve at relatively high breakdown voltages, this conventionally results in high power consumption and significant heating. The presented transmitter circuit is intrinsically robust against these issues, thereby enabling low power operation.@en

A systematic study on the effects of arbitrary parasitic charge profiles, such as trapped or fixed charge, on the 2-D potential distribution in the drain extension of reverse-biased field-plate-assisted reduced surface field (RESURF) devices is presented. Using TCAD device simulations and analytical means, the significance of the so-called characteristic or natural length λ is highlighted with respect to the potential distribution and related phenomena in both ideal (virgin) and nonideal (degraded) extensions. Subsequently, a novel and easy-to-use charge-response method is introduced that enables calculation of the potential distribution for an arbitrary parasitic charge profile once the peak potential and lateral fall-off (∝λ) caused by a single unit charge has been determined. This can be used for optimizing and predicting the performance, also after hot carrier injection, of RESURF power devices.@en

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.@en

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.@en