The instrumentation amplifier, which incorporates Dynamic Element Matching (DEM) and a resistive network, utilizes a digital controller to reduce gain error by means of averaging. This paper assesses the feasibility of combining, within a general-purpose microcontroller, the appealing DEM, i.e., very accurate resistive ratios ranging between 1 and 15, with the associated versatile and scalable interrupt-aware digital controller. Given a mixedsignal system, a hybrid evaluation environment has been developed to perform relevant testbenches for assessing the systems performance, i.e., DEM controller, muxes, OpAmps, with respect to relevant metrics for integrated digital and mixed-signal circuits, i.e., energy, delay, footprint, precision. When implementing our design in a commercial 180nm technology, the gain precision of a typical amplifier is improved by more than 1800 times, with the error converging to as low as 10s of ppm, for Gaussian mismatch distribution between-1% and 1% with the cost of DEM digital circuitry which adds about 30000 µm² of chip area and will consume 194 µA.

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In the context of an artificial intelligence and machine learning landscape that is evolving at an unprecedented pace, we propose a low power, high-speed, mixed-signal graphene nanoribbon-based (GNR) McCulloch-Pitts neuron (MCPN) implementation featuring programmable synaptic weights and inhibitory inputs. By definition, a generic MCPN is comprised of two parts, a weighted summation element and a decision element, called a soma. Our summation element implementation uses three distinct non-rectangular GNR devices, biased under specific conditions, to fulfill the roles of current source, low-side and high-side switches. The programmable excitatory and inhibitory synapses were obtained leveraging GNR SRAM cells and logic gates, hence providing the flexibility needed by real-world applications. The decision element's threshold activation function was implemented using a chain of GNR inverter structures which manifest the function's characteristic in the analog domain. Modulation of the decision element's threshold is achieved indirectly by means of a configurable resistive load which is varied depending on the configuration stored in SRAM. Our benchmark results, obtained using a generic 5 by 5 pixel pattern recognition application, reveal that the GNR-based implementation achieves 3.5× less power consumption, 20 × higher speed, while occupying 3 × less active area when compared to its FinFET analog circuit counterpart.

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The Dynamic Element Matching (DEM) technique's role is to mitigate mismatch issues in complex, matrix-based systems. In this paper, we explore the impact of partially applying DEM to the thermometrically encoded 10-bit most significant bits (MSBs) out of a high-resolution segmented 16-bit Digital-to-Analog Converter (DAC) with the least significant 6 bits being binary encoded. Specifically, we design a general purpose scalable digital control circuit able to employ the DEM algorithm, independent of the matrix dimensions. When implementing the proposed controller using a commercial 180 nm CMOS process, tailored to the 10-bit thermometric decoded DAC MSBs, the integral nonlinearity (INL) 12.63 times lower and the differential nonlinearity (DNL) is 5.8 times lower. The silicon area required for the additional circuitry is around 0.12 mm ², with a power consumption of up to 12.88 mA from a 1.8 V power supply when running at 100 MHz.

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The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays (8-Kbytes up to 128-Kbytes) implemented in various technology nodes. The 3D NEMFETCMOS hybrid dual-port memory is on the average 25% smaller and 8% and 95% larger in terms of footprint when compared to 90nm, 65nm and 45nm CMOS implementations, respectively. The write access time is approximately 2 higher, as it is dominated by the mechanical movement of the NEMFET’s suspended gate, while the read access time is about 12% lower, when compared with 45nm CMOS counterparts. For small size memories our proposal results in at least 15% and 23% energy reductions for 100% and 50% data transition probability, respectively. For large size memories an energy reduction of about 40% was obtained, as in this case the static energy is predominant.@en

The availability of inexpensive and powerful processors provides the means for the computation ecosystem to change its fundamental paradigm towards the Internet of Things (IoT) where ubiquitous nanosystems add intelligence to every object that surrounds us. The new trend for most of those systems is to autonomously operate into a “zero-power” regime, i.e., manage their energy budget in such a way that they can provide the required functionality without any service until they become obsolete. Considering that these systems are most of the time inactive, the static power is the dominant power consumption component, thus the most effective way to fulfill the “zero-power” operation requirement is to diminish the energy consumption into the so called sleep/idle mode. The semiconductor community has been addressing the static power reduction issue at device level, but for the CMOS technology the effectiveness of such approach is limited by the interdependence between static power consumption and device performance. In view of this observation this thesis focuses on improving the energy efficiency of electronic products, battery-powered, and autonomous ones by making use of emerging leakage proof technologies in conjunction with the versatile CMOS counterpart. First, we performed a design space exploration to identify the most promising NEMFET geometries and to evaluate their potential performance in terms of switching delay, current capability, and leakage. Moreover we compared those parameters of interest with the ones offered by traditional transistors utilized in up to date CMOS technologies. Second, we assessed the NEMFET potential when utilized as sleep transistor in circuits featuring 2D cell based power gating, and find out if NEMFETs constitute a viable alternative to High - VTH FETs in sleep mode circuits. Furthermore, we proposed a novel 3D power management approach that attempts to alleviate issues associated with the NEMS utilization as sleep transistor in CMOS power gated integrated circuits. Given the two designs, we evaluated the 2D and 3D NEMFET based power management implementations energy efficiency when embedded into a computation platform executing a bio-medical sensing application. Third, we introduced a NEMFET based logic family tailored to the implementation of ultra-low energy functional units and processors. Fourth, we proposed a memory cell that relies on a NEMFET based inverter designed in such a way that no short circuit current can occur. Finally, we proposed and evaluated the “zero-energy” operation scenario potential of an improved version of the 3D-Stacked NEMS based power management architecture.@en