Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.

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Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.

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This paper proposes a method to calculate the yield of a memristor based sensor array considered as the probability that the chip provides acceptable sensing results when the array is affected by manufacturing defects. The modeling is based on a Markov Chain approach, in which each state represents an operating chip configuration and the state transitions take into account manufacturing defects. The proposed method is applicable to evaluate the yield with different fault models to achieve the comparative yield obtained by several redundancy allocations.

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This article reports the results of fault injection on a microcontroller based on the RISC-V (Riscy) architecture. The fault injection approach uses fault simulation based on Modelsim and targets a set of 1000 fault injected per microcontroller block and per benchmarck. The chosen benchmarks are the Dhrystone and CoreMark that may represent generic workloads. The results show certain block are more prone to fault than others, as also confirmed by a vulnerability analysis that correlates the number of observed faults and the rate of access to the blocks.

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The aim of this paper is to assess the feasibility and on-board hardware performance requirements for on-board telemetry forecasting by implementing a Recurrent Neural Network (RNN) on low-cost multicore RISC-V microprocessor. Gravity field and steady-state Ocean Circulation Explorer (GOCE) public telemetry data was used for training RNNs with different hyperparameters and architectures. The prediction accuracy of these models was evaluated using mean error and R-squared score on the same test dataset. The implementation of the RNN on a RISC-V embedded device, representative of future space-grade hardware, required some adaptations and modifications due to the computational requirements and the large memory footprint. The algorithm was implemented to run in parallel on the 8 cores of the microprocessor and tiling was employed for the weight matrices. Further considerations have also been made for the approximation of sigmoid and hyperbolic tangent as activation functions.@en

This paper presents preliminary position on the use of the novel, free and open RISC-V Instruction Set Architecture (ISA) for on-board electronics in space. The modular nature of this ISA, the availability of a rich software ecosystem, a rapidly growing community and a pool of open-source IP cores will allow Space Industry to spin-in developments from terrestrial fields (in terms of security, artificial intelligence, support for operating systems, hardware acceleration etc.) while focusing its efforts mainly on aspects related to the specific needs of on-board electronics for space applications (e.g. fault tolerance, observability, error signaling, etc.). This will improve reuse and avoid the necessity of developments from scratch when not strategically needed, eventually increasing productivity and reducing costs. The use of an open, non proprietary ISA will allow ad-hoc design of microarchitecture-level soft error countermeasures that can greatly increase the robustness of Application Specific Standard Products (ASSP) and FPGA implementations.

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The tolerance to the cumulative effects of ionizing radiation is one of the most important parameters to keep into account when selecting an EEE component for space applications. TID sensitivity is normally investigated measuring changes induced by gamma rays from 60Co sources to nominal parameters of a component or to its expected functional behavior. In this work we propose an on-chip 90Sr/90Y electron source as an alternative methodology for TID tests.60Co and 90Sr/90Y TID test setups for a complex SoC are compared in terms of complexity and of experimental results, investigating the use of a 90Sr/90Y as well as the established 60Co. We show that 90Sr allows a simpler test setup, manages to reproduce specific modes of failure obtained with 60Co and causes failures at comparable total doses. This makes 90Sr an interesting alternative to 60Co qualification and the use of untested components, to be further investigated especially for complex COTS SoCs.@en

The use of System-on-Chip (SoC) solutions in the design of on-board data handling systems is an important step towards further miniaturization in space. However, the Total Ionizing Dose (TID) and Single Event Effects (SEE) characterization of these complex devices present new challenges that are either not fully addressed by current testing guidelines or may result in expensive, cumbersome test configurations. In this paper we report the test setups, procedures and results for TID testing of a SoC microcontroller both using standard C60o and low-energy protons beams. This paper specifically points out the differences in the test methodology and in the challenges between TID testing with proton beam and with the conventional gamma ray irradiation. New test setup and procedures are proposed which are capable of emulating typical mission conditions (clock, bias, software, reprogramming, etc.) while keeping the test setup as simple as possible at the same time.@en

This paper presents an intended test setup and methodology for testing micro-controller SoCs against the effects of ionizing radiations. The method structure is based on a modular test sequence for test definition, coding, validation and setup. It will be illustrated by the relevant example of a microcontroller solution including lockstep options. Our methodology proposes using low-energy protons for irradiation, and this paper compares this approach with current techniques, showing how proton testing is becoming increasingly interesting, especially for ultra-deep submicron processes in proton dominated environments like low-shielded Low Earth Orbit missions or aircraft avionics. Beyond the convenience of a simplified test setup one of the main advantages of the proton irradiation approach is that it can be used for simultaneous Single Event Effects (SEE) and Total Ionizing Dose (TID) characterization, closer to the "test as you fly" approach.

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This paper discusses radiation tests on complex System-on-Chip (SoC) controllers using Low-Energy Protons (LEPs). The aim of this novel set of guidelines is to be also applicable to System In Package (SIP) or hybrid components that are now often used to overcome printed circuit board's real estate restrictions in Hi-Rel electronics.

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