Is RISC-V ready for Space? A Security Perspective

Conference paper (2022)

Authors

Luca Cassano Politecnico di Milano
S. Di Mascio Space Systems Egineering
Alessandro Palumbo University of Rome Tor Vergata
A. Menicucci Space Systems Egineering
Gianluca Furano European Space Agency (ESA)
Giuseppe Bianchi University of Rome Tor Vergata
Marco Ottavi University of Twente, University of Rome Tor Vergata
Research Group
Space Systems Egineering
Copyright: © 2022 Luca Cassano, S. Di Mascio, Alessandro Palumbo, A. Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi
DOI: https://doi.org/10.1109/DFT56152.2022.9962352
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Published Date

2022

Language

English

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Research Group

Space Systems Egineering

Abstract

Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.

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