This thesis focus on improving the power efficiency of DC-DC converters for two different applications. In the field of implantable medical devices, electrical stimulation has been used as an established treatment for several diseases. It aims to deliver a well-defined amount of charge to the tissue in order to build up a specific electric field and generate or block an action potential. To achieve a large spatial resolution, there is the need for an increasing number of independent stimulating channels to accommodate a large number of stimulating sites. This, however, increases the overall size of the stimulator while potentially affecting the power efficiency. In this respect, the first part of this thesis proposes a multi-channel neural stimulator in which the power efficiency does not depend upon the number of channels being operated simultaneously. On the other hand, in the recently established field of IoT, energy harvesters are increasingly used to ensure a perpetual, but heavily duty-cycled, load operation. However, their typically low output voltage would normally require a boost converter cascaded with a buck converter and low drop-out (LDO) linear regulators to generate multiple supplies of _1V VDD nominal voltage to supply nanoscale CMOS circuits and systems. However, LDOs are noisy, bulky and inefficient. Hence, it seems beneficial for IoT devices to be directly connected to the buck converter. However, the lack of (LDO) isolation exposes supply-sensitive blocks such as LC oscillators to the converter output fluctuations that could severely degrade the system performance. In the second part of this thesis (Chapters 4-6), a noise analysis of a switched-capacitor DC-DC converter reveals that those type of voltage regulators can have an output noise level that is much lower than that of LDOs. They are therefore suitable to power up supply-sensitive blocks. This leads to a new scheme in which an SC DC-DC converter directly powers up an LC oscillator, without consuming additional current or requiring any external component. @en

This article presents guidelines for designing the power supply blocks of RF oscillators. To preserve their spectral purity, the requirements on the noise and ripple of the supply voltage are firstly evaluated based on the oscillator supply pushing factor and the oscillator Figure-of-Merit (FOM). Those specifications are then employed to design and estimate the power efficiency of an analog low-dropout regulator (LDO) and a switched-capacitor DC-DC converter. As a proof of concept, a 2:1 or 3:2 switched-capacitor DC-DC converter is implemented and directly connected to our previously published 4.9-5.5 GHz LC oscillator. The converter provides a 1V supply voltage with a noise ≤0.9nV/√Hz at 1MHz and does not affect the inherent phase noise of the oscillator. The ripple amplitude of the converter is 30mV while its effect is suppressed by the spur reduction block embedded in the oscillator.@en

In this paper, we propose a new scheme to directly power a 4.9-5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/Hz which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to <-65dBc under the 30mVpp ripple of the converter.@en

The total economic cost of neurological disorders exceeds £100 billion per annum in the United Kingdom alone, yet pharmaceutical companies continue to cut investments due to failed clinical studies and risk [1]. These challenges motivate an alternative to solely pharmacological treatments. The emerging field of bioelectronics suggests a novel alternative to pharmaceutical intervention that uses electronic hardware to directly stimulate the nervous system with physiologically inspired electrical signals [2]. Given the processing capability of electronics and precise targeting of electrodes, the potential advantages of bioelectronics include specificity in the time, method, and location of treatment, with the ability to iteratively refine and update therapy algorithms in software [3]. A primary disadvantage of the current systems is invasiveness due to surgical implantation of the device. © 2009-2012 IEEE.@en

This paper presents a novel multichannel level-crossing (MLC) ADC architecture aimed at recording atrial electrograms from multiple channels. The proposed architecture combines synchronous sampling with level-crossing (LC) quantisation to achieve activity dependent operation while recording from multiple channels simultaneously. In the proposed architecture the number of comparisons performed by the quantiser to reach a decision is dependent on the activity of the input signal and is 2-3.3 times lower than that in a conventional SAR ADC. The architecture uses one comparator and one reference level instead of two comparators and two reference levels as in conventional LC ADCs. The proposed architecture is modeled in VerilogA and is designed to be implemented in a standard 0.18 um CMOS process. The MLC ADC converts signals from 4 channels simultaneously and achieves an SFDR of 53.33 dB and an SNDR of 48.96 dB while consuming 9.32 μW of power from a 1.8 V power supply.

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This manuscript points out some mistakes in the Introduction and in the table of comparison of a paper already published in this journal by Hsu and Schmid [1]. Although the main claim of [1] is still preserved, we believe the paper needs to be rectified for scientific correctness of the work. In [1], the first High Frequency Switched-Capacitor (HFSC) stimulator is presented. The stimulation voltage is derived from the main supply by using an 1 : 1 switched-capacitor DC-DC converter. This particular topology of DC-DC converter operates as a resistor [2]. The further away the output voltage is from the input voltage, the lower the power efficiency is. As a result, the output voltage of the DC-DC converter, and therefore the total charge delivered to the tissue, can only be regulated at the expense of the power efficiency. Section I of [1], provides an overview of the most recently published works in the field of electrical stimulation. Based on the stimulation mode, Hsu and Schmid classify the papers into three categories, named voltage-mode stimulation (VMS), current-mode stimulation (CMS) and switched-capacitor stimulation (SCS). In [1], thework presented in [3] has been classified as SCS.However, [3] proposes CMS which adapts the voltage supply of the neurostimulator to the voltage across the electrodes. In [1], the work presented in [4] has been classified as VMS. However, [4] proposes a CMS. In fact, an inductor-based DC-DC converter without the output capacitance is used to deliver the charge to the tissue. Section V of [1] provides a table of comparison, in which the performances of the stimulator circuit are compared with some relevant contributions found in literature. Several errors have been found in the comparison table. The entries in bold characters and red colour of Table I below corrects the table of comparison presented in [1]. II. CONCLUSION The aim of this comment is two-fold. Firstly, it corrects a classification of the most recent works, which was presented in the Introduction of a paper previously published in this journal [1]. Secondly, it corrects some mistakes in its table of comparison. Although errors have been found, the main claim of [1], and hence its scientific contribution, are still preserved. [Table Presented].

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In order to recruit neurons in excitable tissue, constant current neural stimulators are commonly used. Recently, ultra high-frequency (UHF) stimulation has been proposed and proven to have the same efficacy as constant-current stimulation. UHF stimulation uses a fundamentally different way of activating the tissue: each stimulation phase is made of a burst of current pulses with adjustable amplitude injected into the tissue at a high (e.g., 1 MHz) frequency. This paper presents the design, integrated circuit (IC) implementation, and measurement results of a power efficient multichannel UHF neural stimulator. The core of the neurostimulator is based on our previously proposed architecture of an inductor-based buck-boost dc-dc converter without the external output capacitor. The ultimate goal of this work is to increase the power efficiency of the UHF stimulator for multiple-channel operation, while keeping the number of external components minimal. To this end, a number of novel approaches were employed in the integrated circuit design domain. More specifically, a novel zero-current detection scheme is proposed. It allows to remove the freewheel diode typically used in dc-dc converters to prevent current to flow back from the load to the inductor. Furthermore, a gate-driver circuit is implemented which allows the use of thin gate-oxide transistors as high-voltage switches. By doing so, and exploiting the fundamental working principle of the proposed current-controlled UHF stimulator, the need for a high-voltage supply is eliminated and the stimulator is powered up from a 3.5 V input voltage. Both the current detection technique and the gate driving circuit of the current implementation allow to boost the power efficiency up to 300% when compared to previous UHF stimulator works. A peak power efficiency of 68% is achieved, while 8 independent channels with 16 fully configurable electrodes are used. The circuit is implemented in a 0.18 μm HV process, and the total chip area is 3.65 mm²

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In this paper, a power-efficient multiphase Recursive Switched Capacitor (RSC) converter is presented. Conventionally, RSC converters are used to obtain many different output voltages from a fixed input voltage. Here, the converter provides a fixed output voltage of 1 V at 1 mA from an input voltage ranging from 1.4 V to 4.5 V. It has one programmable stage (2:1 or 3:2) followed by four 2:1 stages. Contrary to most conventional topologies, depending on the input voltage, not all the stages are always deployed. This allows to increase the power efficiency of the whole architecture. The flying capacitance of the non-activated stages is transferred to the activated ones. Hence, for any given input voltage, 100 % of the on-chip capacitance is always used for the conversion. For a general 2:1 topology, an analytical analysis of the power losses is carried out and the impact of the overdrive voltage of the switches on the power efficiency is quantified.
A novel gate-driver technique for the switches involved in the conversion is proposed. It ensures an optimal overdrive voltage of the transistor, irrespective of its source and drain potentials. The 16-phase interleaved converter employs a charge recycling technique and uses a total on-chip capacitance of 3 nF.
The RSC converter is designed to be implemented in a standard 40 nm CMOS process which offers a capacitor density of approximately 2 nF/mm^2. Circuit simulations over the whole input voltage range show a power efficiency never lower than 54 % with a peak value of 92.7 %.@en