A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

Conference paper (2022)

Authors

Z. Gao Electronics - EEMCS
Martin Fritz Sony Europe B.V.
J. He Electronics - EEMCS
Gerd Spalink Sony Europe B.V.
R.B. Staszewski Electronics - EEMCS , University College Dublin
S.M. Alavi Electronics - EEMCS
M. Babaie Electronics - EEMCS
Research Group
Electronics (EEMCS) (TU Delft)
Copyright: © 2022 Z. Gao, Martin Fritz, J. He, Gerd Spalink, R.B. Staszewski, S.M. Alavi, M. Babaie
DOI: https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830398
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Published Date

2022

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre-distortion (DPD) and an encoding-assisted (EA)-LMS calibration. While generating a 10MHz 64-PSK signal, the prototype can achieve -46dB EVM with less than one-tenth of the calibration samples (time) required by the prior art.

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