Massively Parallel Analog Front-End Array for Flexible CMOS-based Brain-Computer Interfaces

Abstract

Brain-computer interfaces (BCIs) have the potential to revolutionize human-computer interaction and offer significant biomedical benefits by enabling applications such as closed-loop neuromodulation, mobility restoration for spinal cord injury patients, and therapies for neurodegenerative diseases. To fully leverage BCIs’ capabilities, it is crucial to enhance spatial resolution and robustness by increasing the number of recording channels and expanding brain area coverage. However, current approaches often focus on maximizing the channel count within a single recording analog front-end (AFE), limiting scalability and coverage.

This thesis introduces a novel architecture for a low-power and compact AFE, designed for seamless integration into a massively parallel array of distributed single-channel AFEs dedicated to micro-electrocorticography (μECoG) recording. The proposed AFE features a DC-coupled, chopper-stabilized low-noise boxcar sampler (LNB), followed by a passive switched-capacitor low-pass filter (SC-LPF) and a single-slope (SS) analog-to-digital converter (ADC). The LNB enhances anti-aliasing by introducing notches at multiples of the sampling frequency and effectively reduces chopping ripple. An 8-bit quantization is performed using a continuous time comparator synchronized with a globally distributed ramp across all channels of the array. The SS-ADC achieves a 12-bit resolution at the Nyquist rate (1 kSps) through oversampling at a rate of 16 times (OSR = 16).

Additionally, a novel electrode DC offset (EDO) cancellation loop prevents LNB saturation due to large EDO values, ensuring reliable performance in practical scenarios. Notably, this design eliminates the need for large AC coupling capacitors traditionally used for EDO cancellation, leading to a more compact design and improved scalability for high-density neural recording applications.

The proposed architecture is implemented at the transistor level in 40 nm CMOS technology and extensively validated through simulations. The AFE achieves exceptional area efficiency, with an estimated footprint of only 0.0028 mm² per channel. Moreover, the AFE achieves an input-referred noise (IRN) of 1.69 μV_rms over 0.5-500 Hz and provides an EDO compensation exceeding 100 mVpp. The design exhibits an input impedance of 71.4 MΩ and a common-mode rejection ratio (CMRR) of 80.94 dB. Additionally, the AFE achieves a signal-to-noise ratio (SNR) of 43.3 dB with a 1 mV_pp input signal. These results indicate that the presented AFE architecture, and specifically the novel compensation scheme, represent a promising approach for neural recording applications.