The demand for implementing neural networks on edge devices has rapidly increased as they allow designers to move away from expensive server-grade hardware. However, due to the limited resources available on edge devices, it is challenging to implement complex neural networks. This study selected the Kria SoM KV260 hardware platform due to its affordability and sufficient hardware capabilities for creating a resource-constrained environment. By leveraging the hardware acceleration capabilities of the FPGA for specific nodes of the MobileNetv1 model and offloading other nodes to the onboard quad-core ARM cortex-A53 CPU, it was feasible to implement a neural network on a hybrid combination of CPU and FPGA. Results showed that when executing the MobileNetv1 model in a hybrid configuration, a total runtime improvement of 2.8x over a pure CPU implementation can be achieved. The study concludes that node-wise partitioning of the MobileNetv1 model is a practical solution. This approach offers a cost-effective solution for users who seek an accessible way to run neural networks without the need for expensive server-grade hardware.

Resistive Random-Access Memory (RRAM) is an emerging memory technology that has the possibility to compete with mainstream memory technologies such as Dynamic Random-Access Memory (DRAM) and flash memory. The reason why RRAM has not seen mass adoption yet is due to its defect-prone nature. The resistance of RRAM can assume any value within its operating range and its resistance can be divided into five states instead of the regular two logic states. Conventional test techniques are incapable of detecting unique faults due to their inability to distinguish between all five cell states, resulting in a large number of test escapes. Therefore, new test methods, such as Design-For-Testability (DFT), need to be developed to reduce the number of test escapes and ensure customer satisfaction. This work proposes two new DFTs: Parallel-Reference Read (PRR) and Closed-Loop Write (CLW). The PRR DFT is a replacement for the regular read circuit, which enables the detection of all five cell states, while the CLW DFT is an addition to the regular write circuit, which introduces feedback during the write operation. From these two DFTs, the PRR DFT is selected for further development and its design is validated. From the validation, it is concluded that the PRR DFT can detect all five cell states. Moreover, under process variations, the PRR DFT will provide the correct output in 95.90% of the cases. Furthermore, the PRR DFT improves the overall resistive-defect detection capability by 14.79% when compared to a regular read circuit. Finally, the PRR DFT offers 100% identified fault coverage while only requiring 4N write operations, 5N read operations and an area overhead of 14N_c transistors, where N and N_c are the total number of cells and the total number of columns in the RRAM array, respectively.

The goal of this project is to identify the most promising measurement method and strategy for measuring the thickness of grease and to design a sensor module with electronic read-out and communication module. This project has been split into two parts: a sensor implementation and a communication system. This report describes the design and implementation of the communication module and power supply. The communication module has been designed to work conform a master-slave principle using MODBUS over an RS-485 databus. The used hardware for the communication module is rated to work within a desired 1 to 100m range. Furthermore the master node is connected to the internet to present the data on a small webserver. The power supply design depends on the implementation of the sensor, and contains the use of linear voltage regulators and inverters. The results show that the communication module works properly, whereas the power supply requires some further work.

HedoN is a high-tech electronic development and production company that tasked a group of six TU Delft Electrical Engineering bachelor students to design a simulation system for hydraulic plants. This simulation system consist out of a central Hydraulic Simulation Unit (HSU) that runs a hydraulics simulation and controls various electrical components. This thesis describes the Ethernet communication between that HSU and the electrical components.
As per Requirement 4, the communication system has to be designed to operate on a 1 millisecond tick. Every millisecond the HSU communicates new data with the various electrical components. This data consists of currents, voltages and operation modi for the components. Various Ethernet protocols were considered and in the end raw Ethernet communication on the OSI data link layer was selected. This is the most lightweight possible communications protocol through Ethernet to ensure the communication is fast enough and lightweight on processing power.
Every millisecond the HSU broadcasts a big packet with all the data to every component. These components will then extract information relevant to their operation. This design choice moves the computational effort of selecting relevant data per component from the HSU to the components. This is desirable since the HSU needs enough processing power to run the simulation as well as the communication in parallel. The components will then process the data and provide their response with unicast packets.
For every component to know exactly what data from the broadcasted packet is relevant to them, an initialisation phase is required. This phase is executed before the 1ms tick communication and ensures the components know at what offset they can find their relevant data.
This communication system was then tested to check if it does meet the 1ms requirement. It turns out the communication has some issues achieving the 1ms Requirement 4. The problem could be the non-realtimeness of the Linux kernel running on the HSU which leads to packets not meeting the 1ms requirement. A possible solution to this problem would be to program the HSU on a realtime OS or even baremetal C.

As technology scaling enters the nanometer regime, device aging effects cause quality and reliability issues in CMOS Integrated Circuits (ICs), which in turn shorten its lifetime. Evaluating system aging through circuit simulations is very complex and time consuming. In this thesis, a framework is proposed, which allows for the evaluation of long-term aging effects of ICs and the corresponding measures to counteract premature failure. The focus of this work lies in the abstraction of low-level aging models to system-level models, in order to facilitate swift high-level simulation, without any knowledge of underlying circuit dynamics. Two major aging mechanisms, namely Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) degradation are considered for analysis. System-level aging management is performed with the prototype of a System-on-Chip (SoC) including a Management Unit (MU), which counteracts aging by employing Dynamic Voltage Scaling (DVS), Dynamic Frequency Scaling (DFS), and Adaptive Body Biasing (ABB). The simulation platform prototype is based on System-C AMS and a 65-nm technology library. This SoC simulation computes path delay using characterized models, which represent the aged behaviour of individual circuit elements. Results show that the obtained values are within 2% of circuit-level simulation values at the cost of a simulation time which is 15x lesser than conventional circuit simulators (e.g. Cadence NCSim).