Classical computing has been evolving, to help solve harder problems. Following Moore’s Law the miniaturisation of transistors has helped improve performance. However, this has led to a ”Power Wall”. The clock frequency of processors have not been making the leaps predicted by Moore’s law. This is simply because the power dissipation becomes too high after a certain frequency. This, along with a few other factors, led the industry to move to multi-core processors and continue to homogeneous multi-core systems, multiple cores that are identical to each other, and heterogeneous, multiple cores that are not identical to each other. To further improve performance of computing systems, hardware accelerators were introduced. The one we are all familiar with is the GPU (graphics processing unit). As the name suggests it is an accelerator to process graphics. It is used extensively for image processing and is much faster at doing this than a CPU. There are many more types of hardware accelerators that offers high speedups for certain applications. Quantum accelerators are one such example. There are a certain class of problems that cannot be solved, or rather will take too long to solve on a classical computer, such that it is practically infeasible. One such problem is prime-factorisation problem.

Unitary Decomposition is an algorithm for translating a unitary matrix into many small unitary matrices, which correspond to a circuit that can be executed on a quantum computer. It is implemented in the quantum programming framework of the QCA-group at TU Delft: OpenQL, a library for Python and C++. Unitary Decomposition is a necessary part in Quantum Associative Memory, an algorithm used in Quantum Genome Sequencing. The implementation is faster than other known implementations, and generates $3*2^{n-1}*(2^n-1)$ rotation gates for an n-qubit input gate. This is not the least-known nor the theoretical minimum amount, and there are some optimizations that can still be done to make it closer to these numbers.

The quantum bits (qubits) at the core of any quantum computers are so fragile that quantum error correction(QEC) schemes are needed to increase their robustness and enable fault-tolerant quantum algorithms. The surface code is one of the most popular QEC schemes, but it requires the availability of an efficient decoder. While neural networks have been shown to be well suited to this task, only software implementations have been studied in prior work. These have shown that neural network decoders can be on par or better than other decoding algorithms, but lack the required speed when running as software. The aim of this thesis is to investigate the hardware implementation of the neural networks for the decoders of surface codes to achieve the required speed. Most electronic hardware employed in quantum computers today operates at room temperature and is connected by bulky wires to the qubits, which are placed in a cryogenic chamber for proper operation. Since any useful quantum computer will comprise thousands or even millions of qubits, this work proposes to also move the QEC hardware to cryogenic temperatures (4 K). However, because at these temperatures the cooling power of cryogenic refrigerators is limited, the hardware needs to be low power, while ensuring enough speed to keep the pace of the QEC. The exploration of this work sweeps multiple parameters of a feed-forward neural network to find what the influence is on the decoder performance and the delay, the power, and the area. The parameters that are swept are the number of hidden layers, their sizes, the type of transfer functions and the number of bits used in the quantization of the weights and outputs. The results show that using the configurations found in this work it is possible to meet the performance and timing constraints using cryo-CMOS on both an FPGA and in a 40-nm technology. Although there are still some limitations in this work, such as the scaling in the power consumption and decoding performance for larger distances, there are multiple proposed improvements, making this is a stepping stone towards a future scalable implementation of QEC.

Quantum Computing is an emerging field of technology with the promise that engineered quantum systems can address hard problems such as, problems with exponential compute complexity in Chemistry, Genomics, Optimization and many more applications. Quantum Computer Architecture is an area of research targeted for the NISQ-era quantum computing and little research has been done for development of a scalable classical control and read-out infrastructure for the quantum processors. The project is aimed at study of SoC-FPGA design methodology and architecture design for control of quantum processor. The targeted quantum hardware is the Spin-Qubit in Semiconductor Quantum Dot Chip. The project is intended for understanding the design and working of a silicon-spin qubit for a computer (architecture) engineer. It further helps identify necessities for an architecture, Instruction Set requirements, bottlenecks and future challenges (specific to Spin-Qubit quantum processor) that would help in better designs for new control architectures.

The objective of this thesis is directed towards addressing the architectural challenges for the quantum-classical hardware for controlling the NISQ-era quantum devices and beyond. We analyze the control infrastructure requirements and propose a micro-architecture and waveform generation methodology to integrate the physical device with the quantum compilation tool-chain.

The goal of this thesis is the design and development of the QuTech Central Controller, a system conceived to serve as the hardware/software interface of a quantum computer. This system represents an evolution of the QuMA microarchitecture to control a Surface-17 superconducting quantum processor, even though several architectural mechanisms are used to ensure the compatibility of the design with different quantum hardware technologies. In addition to an expansion of the control microarchitecture, the QuTech Central Controller represents an evolution of the overall system architecture, making use of a different hardware infrastructure to overcome previous scalability limitations.

The main contributions of this thesis are a proposed centralized microarchitecture capable of controlling up to 17 qubits, the implementation of this microarchitecture in a device called the QuTech Central Controller and its testing in dynamic quantum information processing experiments with superconducting qubits.

Developments in sequencing technology have drastically reduced the cost of DNA sequencing. The raw sequencing data being generated requires processing through computationally demanding suites of bioinformatics algorithms called genomics pipelines. The greatly decreased cost of sequencing has resulted in its widespread adoption, and the amount of data that is being generated is increasing exponentially, projected to soon rival big data fields such as astronomy. Therefore, acceleration and optimization of such genomics pipelines is becoming increasingly important.

The BWA-MEM genomic mapping algorithm is a critical first step of many genomics pipelines, as it maps the raw input sequences onto a reference genome, thereby reconstructing the sample's original genetic assembly. A major part of overall BWA-MEM execution time is spent performing Seed Extension, an algorithm closely related to the Smith-Waterman pairwise sequence alignment algorithm. The standard approach for the heterogeneous acceleration of the Smith-Waterman algorithm is to map it onto a systolic array architecture to compute elements of the similarity matrix in parallel. In order for systolic arrays to operate at high efficiency, they require long sequences to be aligned to one another. The BWA-MEM algorithm, in contrast, typically generates very short sequences that then require pairwise alignment through the Seed Extension algorithm. Therefore, in this dissertation, various techniques to improve the efficiency of systolic arrays for short sequence lengths are proposed.

The Variable Logical Length, the Variable Physical Length, and the Variable Logical and Physical Length systolic array architectures are proposed to eliminate the dependence of systolic array efficiency on read sequence length. To eliminate its dependence on reference sequence length, a streaming, implicit synchronizing architecture is introduced. Together, these techniques result in a maximally-efficient systolic array. A Seed Extension kernel has been implemented on both FPGA and GPU with a threefold kernel-level improvement to execution time, resulting in the first FPGA-accelerated and the first GPU-accelerated implementation of BWA-MEM with an overall end-to-end twofold application-level speedup. Moreover, a Smith-Waterman implementation has been developed on FPGA using the above efficiency improvements to the systolic array architecture, resulting in an implementation that has a performance of 214 GCUPS and that is able to attain 99.8% efficiency, which is the highest reported efficiency and performance of any FPGA-accelerated Smith-Waterman implementation to date. Finally, various aspects of these designs are evaluated, including power-efficiency and design-time.@en

Quantum microarchitecture is a key component in bridging the gap between quantum software and quantum hardware of a fully programmable quantum computer. Confronting the control problem of superconducting quantum processors, an experimental microarchitecture (QuMA) has been proposed in previous work. As the size of the target quantum chip continues to evolve, the complexity of QuMA scales up accordingly. This increase in complexity has led to a growing challenge in QuMA’s design, development, and verification. To solve these problems, we build a QuMA simulator which can automate the current QuMA verification process and accelerate the design phase of QuMA. We called this simulator QuMAsim. The first version of QuMAsim is based on CC-Light, an instance of QuMA for controlling a surface-7 superconducting qubit chip. Then this simulator is extended to be self-configurable for different quantum chips. Several applications are built based on this simulator. The verification platform consists of the simulator, the VHDL implementation of QuMA and a validator is designed to automate the verification procedure. In addition, we built a quantum virtual machine based on QuMAsim, which includes other quantum software and simulators to simulate the execution of quantum algorithms on each layer of the quantum computer. We demonstrate the potential of QuMAsim by performing some experiments with it and its applications, including the gearbox circuit simulation.

Fast sequencing and analysis of (microorganism, plant or human) genomes will open up new vistas in fields like personalised medication, food yield and epigenetic research. Current state-of-the-art DNA pattern matching techniques use heuristic algorithms on computing clusters of CPUs, GPUs and FPGAs. With genomic data set to eclipse social and astronomical big data streams within a decade, the alternate computing paradigm of quantum computation is explored to accelerate genome-sequence reconstruction. The inherent parallelism of quantum superposition of states is harnessed to design a quantum kernel for accelerating the search process. The project explores the merger of these two domains and identifies ways to fit these together to design a genome-sequence analysis pipeline with quantum algorithmic speedup. The design of a genome-sequence analysis pipeline with a quantum kernel is tested with a proof-of-concept demonstration using a quantum simulator.

The trend of computing faster and more efficiently has been a driver for the computing industry since its beginning. However, it is increasingly difficult to continue this trend because current CMOS technology cannot be down-scaled anymore due to physical restrictions. Consequently, to obtain the next major performance improvement, the focus is shifting from a technology-only optimization effort towards a system-level hardware-software co-design optimization strategy. In recent years, the move to heterogeneous computing has gained enormous traction with all the big names such as Intel, IBM, and NVIDIA investing heavily in this approach. This paradigm shift is characterized by traditional general-purpose processors offloading data to hardware accelerators, which are capable of exploiting parallelism to a significantly higher degree. An accelerator which has existed for decades but has recently risen to greater prominence is the field-programmable gate array (FPGA). The scientific computing community is also experiencing the need for higher computational power as their problem sizes increase. FPGAs make a promising candidate for their ability to tailor complex algorithms to specialized hardware circuits. A key algorithm to accelerate in this domain is the Sparse Matrix Vector Multiplication (SpMV). There do not exist many HLS (High-Level Synthesis) designs for this kernel, and the one designed using Vivado HLS exhibits significantly lower performance than the state-of-the-art. We argue that the most effective way to achieve speedup is by implementing multiple parallel pipelines so that multiple result values are produced in each cycle. Consequently, we develop an implementation agnostic partitioning algorithm for SpMV that splits the problem into independent streams. The HLS kernel performs well as a standalone unit, offering a speedup of up to 150x compared to the ARM coprocessor on the ZYNQ system and up to 4.6x to state-of-the-art Vivado HLS-based solutions. Our estimations show that the solution scales with an increasing number of resources.

Quantum algorithms can be described by quantum circuits which consist of quantum bits (qubits) and quantum gates. Such a circuit description assumes that any kind of interaction between qubits is possible. However, quantum chips have limited qubits connectivity only allowing, for instance, nearest-neighbor (NN) interactions. That means, qubits need to be placed in adjacent positions for performing a two-qubit gate. In this thesis, a routing algorithm is proposed where physical qubits or planar-based logical qubits are routed to obey this nearest neighbor constraint in a 2D qubit topology. This algorithm tries to minimize the circuit latency or communication overhead.

The proposed routing algorithm is based on a sliding window principle. Different paths, found by using an adapted breadth-first search algorithm, are evaluated based on the interleaving of the corresponding routing instructions, e.g., SWAP operations with previous instructions, and by looking at the disordering of future qubits. The path that will add the lowest number of cycles to the algorithm is then selected and efficiently inserted with the rest of the instructions. This process continues until all the instructions inside the quantum algorithm obey the nearest neighbor constraints.

The routing algorithm is tested for several real quantum algorithms taken from QLib and ScaffCC, as well as for random generated benchmarks. Taking different alternative paths into account and evaluating those paths for possible interleaving with previous instructions, always has a positive effect to minimize the number of added cycles. The results concerning the evaluation of the disordering of future qubits could have a positive or negative effect on the circuit latency depending on the quantum circuit.