In this paper, a fixed-point finite impulse response adaptive filter is proposed using approximate distributed arithmetic (DA) circuits. In this design, the radix-8 Booth algorithm is used to reduce the number of partial products in the DA architecture, although no multiplication is explicitly performed. In addition, the partial products are approximately generated by truncating the input data with an error compensation. To further reduce hardware costs, an approximate Wallace tree is considered for the accumulation of partial products. As a result, the delay, area, and power consumption of the proposed design are significantly reduced. The application of system identification using a 48-Tap bandpass filter and a 103-Tap high-pass filter shows that the approximate design achieves a similar accuracy as its accurate counterpart. Compared with the state-of-The-Art adaptive filter using bit-level pruning in the adder tree (referred to as the delayed least mean square (DLMS) design), it has a lower steady-state mean squared error and a smaller normalized misalignment. Synthesis results show that the proposed design attains on average a 55% reduction in energy per operation (EPO) and a 3.2\times throughput per area compared with an accurate design. Moreover, the proposed design achieves 45%-61% lower EPO compared with the DLMS design. A saccadic system using the proposed approximate adaptive filter-based cerebellar model achieves a similar retinal slip as using an accurate filter. These results are promising for the large-scale integration of approximate circuits into high-performance and energy-efficient systems for error-resilient applications.

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This paper proposes the design of an adaptive filter in stochastic circuits. The proposed circuit requires lower area and power than a conventional stochastic implementation. In the proposed design, the stochastic multiplier is implemented by an XNOR gate, as in a conventional scheme. However, the stochastic adder based on a multiplexer is not a very efficient implementation due to the three required stochastic number generators (SNGs) and the iterative operation required in the adaptive filter. Thus, a novel stochastic adder using a counter and a post processing unit is proposed. This adder avoids the use of SNGs, therefore it incurs a smaller area and power, while operating faster than the conventional (multiplexer-based) stochastic adder. In terms of accuracy and hardware efficiency, simulation results show that the adaptive filter using the proposed stochastic design outperforms the conventional stochastic implementation using linear feedback shift register (LFSR) based SNGs. Specifically, the proposed design consumes 35.81% less dynamic power and 21.34% less area than an LFSR-based implementation at a slightly higher accuracy.@en

The achievements of quantum computation theory, e.g. Shor's factoring algorithm, motivate efforts to realize quantum computers. Among systems proposed for quantum computing macroscopic superconducting circuits of Josephson junctions appear promising for integration in electronic circuits and large-scale applications. Recently, a superconducting tunnel junction circuit was designed and a sufficiently high quality factor of quantum coherence has been obtained. This indicates that decoherence need not be among the obstacles in building quantum computers with macroscopic Josephson circuits. In this paper we present the setup of some elementary quantum logic with macroscopic Josephson qubits, strengthened by some simulation work, and then study the feasibility of implementing Shor's quantum factoring algorithm on them. It is shown that it would be eventually possible to build a 2-Dimensional Josephson qubit array, possibly accompanied by classical computing components, capable of performing useful quantum computations.@en

In order to make systems based on nanometerscale devices reliable, the design of faulttolerant architectures will be necessary. This paper presents a novel faulttolerant technique for future nanocomputers, NAND multiplexing. Initiated by von Neumann, the NAND multiplexing technique, based on a massive duplication of imperfect devices and randomized imperfect interconnect, had been studied with an extreme high degree of redundancy (A 4333). In this paper, the NAND multiplexing is extended to rather low degree of redundancy, leading it to a comprehensive faulttolerant theory. The stochastic Markov nature in the heart of the system is discovered, and the characteristics of such a Markov chain are exploited. This faulttolerant technique is potentially useful for future nanoelectronics. Keywords: Markov Process, Normal Distribution, Binomial Distribution@en

A superconducting qubit (or quantum bit), which consists of a micrometer-sized loop with three Josephson junctions, has two persistent currents of opposite direction as its two states. The states of the qubit can be brought into quantum coherence to perform quantum computing. Classical bits can also be obtained from these superconducting loops, making it possible to base a classical computer architecture. We study a novel computing structure based on these Josephson Persistent Current (PC) Bits, starting from elementary logic gates to a Random Access Memory (RAM). The investigation shows that the Josephson PC Bit technology would not surpass semiconductor technology in term of the device density, while it is a promising candidate for unltra-fast memory, which can be integrated with other technologies. The classical computer might also serve as pre and post processor for the quantum computing performed in the heart of the array. The Josephson PC circuits, therefore, seems a good vehicle for the study of the quantum computer paradigm. Keywords: computing architecture, Josephson, circuit simulation, classical computing, quantum computing@en