Functional ultrasound (fUS) is a relatively new imaging modality to study the brain with a high spatiotemporal resolution and a wide field-of-view. In fUS detailed images of cerebral blood flow and volume are used to derive functional information, as changes in local flow and/or volume may reflect neuronal activation through neurovascular coupling. Most fUS studies so far have been performed in rats. Translating fUS to mice, which is a favorable animal model for neuroscience, pleads for a higher spatial resolution than what has been reported so far. As a consequence the temporal sampling of the blood flow should also be increased in order to adequately capture the wide range in blood velocities, as the Doppler shifts are inversely proportional to the spatial resolution. Here we present our first detailed images of the mouse brain vasculature at high spatiotemporal resolution. In addition we show some early experimental work on tracking brain activity upon local electrical stimulation.@en

The cardiac interpulse interval (IPI) has recently been proposed tofacilitate key exchange for implantable medical devices (IMDs) using apatient's own heartbeats as a source of trust. While this form of key exchangeholds promise for IMD security, its feasibility is not fully understood due tothe simplified approaches found in related works. For example, previouslyproposed protocols have been designed without considering the limitedrandomness available per IPI, or have overlooked aspects pertinent to arealistic system, such as imperfect heartbeat detection or the energy overheadsimposed on an IMD. In this paper, we propose a new IPI-based key-exchangeprotocol and evaluate its use during medical emergencies. Our protocol employsfuzzy commitment to tolerate the expected disparity between IPIs obtained by anexternal reader and an IMD, as well as a novel way of tackling heartbeatmisdetection through IPI classification. Using our protocol, the expected timefor securely exchanging an 80-bit key with high probability (1-10−6) is roughlyone minute, while consuming only 88 μJ from an IMD.@en

Permanent faults on a chip are often tolerated using spare resources. In the past, sparing has been applied to Chip Multiprocessors (CMPs) at various granularities of substitutable units (SUs). Entire processors, pipeline stages or even individual functional units are isolated when faulty and replaced by spare ones using flexible, reconfigurable interconnects. Although spare resources increase systems fault tolerance, the extra delay imposed by the reconfigurable interconnects limits performance. In this paper, we study two options for dealing with this delay: (i) pipelining the reconfigurable interconnects and (ii) scaling down operating frequency. The former keeps a frequency close to the one of the baseline processor, but increases the number of cycles required for executing a program. The latter maintains the number of execution cycles constant, but requires a slower clock. We investigate the above performance tradeoff using an adaptive 4-core CMP design with substitutable pipeline stages. We retrieve post place and route results of different designs running two sets of benchmarks and evaluate their performance. Our experiments indicate that adding reconfigurable interconnects for wiring the SUs of a 4-core CMP pose significant delay increasing the critical path of the design almost by 3.5 times. On the other hand, pipelining the reconfigurable interconnects increases cycle time by 41% and - depending on the processor configuration - reduces performance overhead to 1.4-2.9× the execution time of the baseline.

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