We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P⁺/Deep N-well junction with a circular shape, for which N-well is intentionally excluded to achieve a wide depletion region, thus enabling lower tunneling noise and better timing jitter as well as a higher photon detection efficiency and a wider spectrum. In order to prevent premature edge breakdown, a P-type guard ring is formed at the edge of the junction, and it is optimized to achieve a wider photon-sensitive area. In addition, metal-1 is used as a light reflector to improve the detection efficiency further in backside illumination. With the optimized 3-D stacked 45-nm CMOS technology for back-illuminated image sensors, the proposed SPAD achieves a dark count rate of 55.4 cps/μm² and a photon detection probability of 31.8% at 600 nm and over 5% in the 420-920 nm wavelength range. The jitter is 107.7 ps full width at half-maximum with negligible exponential diffusion tail at 2.5 V excess bias voltage at room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3-D stacked SPAD technologies.

@en

We investigate the effects of parasitic resistance on the performance of silicon avalanche photodetectors (APDs) fabricated in the standard complementary metal-oxide-semiconductor (CMOS) technology. Two types of CMOS-APDs based on the P+/N-well junction having two different parasitic resistances are realized, and their current-voltage characteristics, responsivities, avalanche gains, photodetection frequency responses, and electrical reflection coefficients are measured and compared. In addition, the effect of parasitic resistance on the photodetection bandwidth is analyzed with an equivalent circuit model. It is clearly demonstrated that the parasitic resistance has great effects on the gain and photodetection bandwidth of CMOS-APDs.@en

This letter reports on the first silicon avalanche photodetectors (APDs) with over 10-GHz bandwidth. Three types of APDs based on P+/N-well junction are realized in standard complementary metal-oxide-semiconductor (CMOS) technology. For bandwidth improvement, the CMOS-compatible APDs (CMOS-APDs) are designed to be smaller active area, and a spatially-modulated avalanche photodetector (SM-APD) is also proposed in order to further reduce the bandwidth limiting factor of the CMOS-APDs. Current-voltage characteristics, responsivities, and photodetection frequency responses of the three APDs are measured and compared, and the photodetection bandwidth characteristics are analyzed with an equivalent circuit model to identify the origin of the bandwidth improvement. The proposed small-area CMOS-APD provides 10-GHz bandwidth with high responsivity, and the SM-APD achieves 12-GHz bandwidth, which is the largest bandwidth ever reported for silicon photodetectors in standard CMOS technology.@en