There is a great increasing demand to embed GNSS receivers on portable devices, because they can provide much higher positioning accuracy and better availability compared with GPS-only receivers. However, portable devices have strong limitations on power consumption and area. In order to realize a low power and compact GNSS receiver, this paper presents both system level and circuit level solutions. In the system level, a two-state GNSS receiver architecture is introduced with acquisition phase and tracking phase to optimize the power consumption. In the circuit level, a dual-mode inductorless LNTA with adaptive bias and with an active inductor for gain boosting is proposed. This LNTA is designed and layout in a 40nm CMOS technology.

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This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.@en

This contribution presents the development of an integrated power combiner in Bi-CMOS technology employing artificial dielectric layers (ADLs) at submillimeter wave frequencies. The power is gathered from frequency multiplier chains into a single waveguide which is loaded with ADL in order to reduce the structure footprint.@en