A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement

Journal article (2017)

Authors

Yang Liu Southeast University

Zhiqun Li Southeast University

H. Gao Electronics - , Eindhoven University of Technology, Southeast University

Qin Li Southeast University

Zhigong Wang Southeast University

Research Group

Electronics () (TU Delft)

CMOS Negative resistor Complementary push-push Frequency doubler

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http://resolver.tudelft.nl/uuid:853e27d6-c723-4aa6-a049-c2747b547342

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Published Date

01-01-2017

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.

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