In order to improve the ability to design digital ICs for cryogenic temperatures, the objective of this work is to characterize the timing performance of standard cells in the TSMC 40nm technology at a temperature range between 4K and 300K. A design was made to perform automated
...
In order to improve the ability to design digital ICs for cryogenic temperatures, the objective of this work is to characterize the timing performance of standard cells in the TSMC 40nm technology at a temperature range between 4K and 300K. A design was made to perform automated on-chip characterization of standard cell propagation delay, that makes use of random sampling. An ASIC was implemented and fabricated based on this design. A test setup was designed and build to perform the characterization. Besides that a design for a scalable gray-counter was developed and implemented that promises excellent performance for power critical applications.
