This paper presents a sub-1V delta-sigma modulator (DSM) with power and bandwidth (BW) scalability for IoT applications. It is built around a fully dynamic and low-voltage floating inverter amplifier (LVFIA). To extend the power and BW scalability of the LVFIA, its relatively supply-independent bias current is auto-controlled by DSM's sampling frequency f_s. Dynamic techniques such as auto-zeroing and chopping are applied to achieve low noise. Fabricated in a 130nm CMOS, the proposed sub-1V DSM shows a near-consistent SNDR (90dB) and linearly scalable power and BW (2.5nW/Hz) over a ×30 scaling range of f_s. It achieves Walden FoM and Schreier FoM of 51.3fJ/conv-step and 175.7dB, respectively.

This article presents a compact sub-1-V bipolar junction transistor (BJT)-based temperature sensor for thermal management applications. To operate from a sub-1-V supply, two capacitors are first pre-charged to a supply-independent initial voltage (> 1 V) by regulated charge pumps (RCPs) and then discharged through two diode-connected BJTs. By using different discharge times, proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages can be generated. These are then read out by an area-and energy-efficient charge-balancing ΔΣ modulator to generate a digital representation of temperature. To reduce its noise, the modulator's first inverter-based integrator employs both chopping and auto-zeroing. Fabricated in a standard 22-nm bulk CMOS process, the sensor occupies 0.01 mm² and consumes 2.9 μW from a 0.8-V supply. It achieves a 1-point trimmed inaccuracy of ± 0.4 °C (3σ) from -40 °C to 125 °C, which is the best reported in sub-65-nm CMOS. It also achieves high energy efficiency, resulting in a resolution figure of merit (FoM) of 0.41

This article presents a 14-bit fully dynamic sensor interface that consists of a switched-capacitor (SC) ΔΣ modulator and a dynamic bandgap reference (BGR). The BGR is implemented by summing the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) outputs of two PNP-based capacitive DACs. At the sampling rate, the DAC capacitors are pre-charged to the supply and then discharged for a fixed period via PNPs, thus biasing them and simultaneously sampling their base-emitter voltages. By using the modulator's first integrator to sum the DAC outputs, a dynamic BGR can be realized, which does not need additional reference buffers or decoupling capacitors. To make the system fully dynamic, the modulator itself is based on capacitively biased (CB) floating inverter amplifiers (FIAs). Implemented in a standard 130-nm CMOS process, the sensor interface occupies an area of 0.2 mm². It achieves an SNDR of > 84.5 dB over a scalable bandwidth (BW) ranging from 98 Hz to 5.9 kHz while consuming 1.7-50.8 μW. Furthermore, by employing a time-domain temperature-compensation scheme, it achieves a batch-trimmed gain error of ± 0.26% from -40°C to 125 °C.

This letter presents a low-power dB-linear variable gain amplifier (VGA) with a small linear-in-dB error over a wide gain tuning range. An exponential current ratio is realized in the linear-in-dB control circuit based on the subthreshold I-V characteristic. The VGA is built with subthreshold common-gate transistors as current steering, accurately replicating the exponential current ratio and forming a tunable gain. Implemented in 55-nm CMOS technology, the proposed VGA occupies a compact active area of 0.011 mm2 excluding the buffer. It achieves a linear-in-dB error of 0.4 dB over a gain tuning range of 62.4 dB, corresponding to the state-of-the-art relative error of 0.6%. The proposed design shows constant 80-MHz bandwidth with a power consumption of 0.96 mW.

This brief presents a 0.65% relative inaccuracy CMOS temperature sensor with a duty-cycle-modulated (DCM) output. It uses a BJT-based front-end to generate a proportional to absolute temperature voltage (V_{PTAT}) and a complementary to absolute temperature voltage (V_{CTAT}), which are then modulated to a digital-friendly duty-cycle output. Dynamic element matching with Kelvin connection (KC-DEM) is applied to improve the accuracy of V_{PTAT}. To enhance the robustness of the sensor, a continuous-time dynamic single-threshold hysteresis comparator with high energy efficiency is proposed. Implemented in a standard 0.13-{m} CMOS process, the sensor has an active area of 0.086 mm2 and achieves an inaccuracy of ±0.54 °C (3) from -40 °C to 125 °C.

This work presents an energy-efficient diode-based CMOS temperature sensor. It is based on the capacitively biased diode (CBD) working principle and can operate with a 1-V supply voltage. Instead of using a separate CBD front-end and ADC, a new architecture is proposed in which the CBD front-end is directly embedded into the 1st stage of a 1-bit 2nd-order switched-capacitor ΣΔ-ADC, thereby improving both energy efficiency and accuracy. The circuit was fabricated in a standard 55-nm CMOS process and occupies an active area of 0.021 mm². The measured inaccuracy is ±0.6 °C (3σ) from -55 °C to 125 °C after a 1-point calibration. Furthermore, it consumes 2.2 μW and achieves a resolution of 15 mK in a conversion time of 6.4 ms, which corresponds to a competitive resolution FoM of 3.2 pJ·K²