J

JY Hur

14 records found

Authored

Comparative analysis of soft and hard on-chip interconnects for FPGAs
Journal article (2012) - JY Hur, K.G.W. Goossens, L. Mhamdi, M.A. Wahlah

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
Journal article (2012) - JY Hur, T.P. Stefanov, J.S.S.M. Wong, K.G.W. Goossens

Customizing and Hardwiring On-chip Interconnects in FPGAs
Doctoral thesis (2011) - JY Hur

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices
Conference paper (2010) - TM Thomas, JY Hur, K.L.M. Bertels, G. Gaydadjiev

Design trade-offs in customized on-chip crossbar schedulers
Journal article (2008) - JY Hur, J.S.S.M. Wong, T.P. Stefanov

Hardwired networks on chip in FPGAs to unify functional and configuration interconnects
Conference paper (2008) - K.G.W. Goossens, M Bennebroek, JY Hur, M.A. Wahlah

Performance analyses of soft and hard single-hop and multi-hop circuit-switched interconnects for FPGAs
Conference paper (2008) - JY Hur, K.G.W. Goossens, L. Mhamdi

FPGA Implementation of Parallel Histogram Computation
Conference paper (2008) - A. Shahbahrami, JY Hur, B.H.H. Juurlink, J.S.S.M. Wong

Partilially reconfigurable point-to-point FPGA interconnects
Journal article (2008) - JY Hur, J.S.S.M. Wong, S Vassiliadis

Customizing reconfigurable on-chip crossbar scheduler
Conference paper (2007) - JY Hur, T.P. Stefanov, J.S.S.M. Wong, S Vassiliadis

Partially reconfigurable point-to-point interconnects in virtex-II pro FPGAs
Conference paper (2007) - JY Hur, J.S.S.M. Wong, S Vassiliadis

Systematic customization of on-chip crossbar intervconnects
Conference paper (2007) - JY Hur, T.P. Stefanov, J.S.S.M. Wong, S Vassiliadis

Parallel merge sort on a binary tree on-chip network
Conference paper (2005) - J.S.S.M. Wong, S Vassiliadis, JY Hur

Implementation of a dual analog decoder
Conference paper (2004) - JY Hur, J.S.S.M. Wong, S.D. Cotofana