Analog-to-digital converters are important blocks in any electronic system which act as a bridge between analog signals and digital processors. The conventional SAR ADC employs a binary search algorithm and has emerged as the most suitable solution for low-power applications, due to its excellent power efficiency. The proposed ADC architecture incorporates a new design approach which combines the high resolution capabilities of oversampled ADCs with a 5-bit configuration asynchronous SAR ADC. In this thesis, the theory, analysis and design of a 2nd order error feedback noise shaping SAR are addressed. The underlying concept of the error feedback topology is to optimize the location of complex zeros in the noise transfer function and improve the SQNR for a lower sampling frequency. The stringent power and area budget imposes challenges in designing active blocks with a low transistor count. The impact of a new switching scheme for the capacitive DAC is examined analytically while considering the trade-off between linearity and power savings. The design uses a small assisting SAR and reaches 96% improvement in power consumption due to switching when comparing to a conventional scheme. The converter operates at 1 MHz and consumes 11 $\mu$W, from a 1.8 V supply. In a bandwidth of 20 kHz and an OSR of 25, it achieves an SNDR of 71 dB, an ENOB of 11.5 bits and a Walden FOM of 98 fJ/conversion-step.