Over the last fifty years Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down, making the design of high-performance applications possible. However, there is a growing concern that device scaling will become infeasible below a certain feature size. In parallel, emerging applications present high demands regarding storage and computing capability, combined with challenging constraints. In this scenario, memristive devices have become promising candidates to replace or complement CMOS technology due to their CMOS manufacturing process compatibility, zero standby power consumption as well as high scalability and density. Despite these advantages, the implementation of high-density memories based on memristive devices poses some challenges related manufacturing process variation and consequently, to their reliability during lifetime. This paper investigates the impact of manufacturing process variation on Resistive Random Access Memories (RRAMs). In more detail, an evaluation of the RRAM's functionality when considering different levels of manufacturing process variation is performed. The obtained results show that different parameters can degrade the functionality of the RRAM cell as well as that there is a relation between the performed operating sequence and the tolerated percentage of variability. Finally, it is important to mention that understanding how process variation impacts the functionality of RRAM cells is considered essential to guarantee their reliability during lifetime, also allowing to optimize manufacturing processes.@en

Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

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