“Medium-entropy” highly disordered amorphous Li garnets, with ≥4 unique local bonding units (LBUs), hold promise for use as solid-state electrolytes in hybrid or all-solid-state batteries owing to their grain-boundary-free nature and low-temperature synthesis requirement. Through this work, we resolved the local structure of amorphous Li garnet and understood their implication for Li dynamics. These medium-entropy amorphous structures possess unique characteristics with edge- and face-sharing LBUs, not conforming to the classic Zachariasen glass formation rules, and can be synthesized in a wide but processing-friendly temperature range (<680°C). Within these amorphous structures, Li and Zr are identified as the network formers and La as network modifier, with maxima in Li dynamics observed for smaller Li–O and Zr–O coordination; this structure understanding serves as a baseline for identifying additional network formers to further modulate Li transport. Our insight provides fundamental guidelines for the structure and phase design for amorphous Li garnets and paves the way for their integration in next-generation batteries.

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In-memory computing promises to overcome memory and power walls by allowing efficient computing of operations inside the memory without the need to explicitly transfer operands back and forth to the processor core. This paradigm is enabled by emerging resistive memory technology and the adjustment of the memory periphery to perform the computation. The existing methods to perform in-memory calculations are either bound to a specific technology or do not scale well for complex multi-input functions. In this article, we propose a new technique for in-memory computing using resistive devices to calculate the symmetric Boolean logic operations for any number of inputs. In our proposed method, we first convert the equivalent resistance state that is generated by storing devices to an electrical oscillation, and later, time-based sensing for these oscillations is employed to generate the required output. Since the computation using our proposed technique is based on the oscillations, it can be easily tuned for different computation tasks depending on applications. This is used to implement an efficient column-wise error-correction code (ECC) for in-memory computing. We have performed extensive Monte Carlo simulations to confirm the functionality of our proposed method in the presence of process variation. Compared with state-of-the-art comparative-based schemes, for a two-bit in-memory XOR computation, our proposed technique can improve dynamic energy by 41% and additionally scales well for more number of inputs. Results show a reduction of the parity overhead by 10% in our evaluated memory and an area reduction of 21% compared with conventional ECC circuits.@en