The continuous transistor scaling and extremely lower power constraints in modern VLSI chips can potentially supersede the benefits of the technology shrinking due to reliability issues. Due to external aggression factors, e.g., radiation and temperature gradients, the CMOS devices flawless functioning cannot be guaranteed any more. Thus, design time Integrated Circuits (ICs) reliability assessment is now turning out to be a mandatory step in the IC design flow. In this work, we present a novel CAD analytical error/reliability propagation analysis technique called Conditional Probabilistic Error/Reliability Propagation Analysis (CPERPA) algorithm. CPERPA efficiently resolves reliability related correlations including reconvergent fanouts and related errors, using a condition algorithm originating from the conditional probability theory, which promotes the accuracy at the expense of relatively low complexity enhancement. Experimental results on several benchmark circuits demonstrate the accuracy and the simulation time advantages of our approach when compared to Monte-Carlo simulations. The results obtained with the proposed CPERPA framework are within 3% average error and up to 1000 times faster when compared to Monte-Carlo simulations.@en

With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition to size, performance, and energy. In this paper, a supply voltage Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSI circuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. The experimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic enchmark circuits. @en