A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

Conference paper (2016)

Authors

Bo Yang University College Cork

E Popovici University College Cork

Michael Alan Quille University College Cork

Andreas Amann University College Cork

S.D. Cotofana Computer Engineering -

Research Group

Computer Engineering () (TU Delft)

Reliability VLSI Statistical Timing Analysis Delay Estimation Delay PDF Propagation

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Published Date

2016

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition to
size, performance, and energy. In this paper, a supply voltage Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSI
circuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. The
experimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic enchmark circuits.