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AJ van de Goor

49 records found

MBIST architecture framework based on orthogonal constructs

New algorithms for address decoder delay faults and bit line imbalance faults

Defect oriented testing of the strap problem under process variations in DRAMs

DRAM-specific space of memory tests

Opens and delay faults in CMOS RAM address decoder

Space of DRAM fault models and corresponding testing

Memory test experiment: industrial results and data

Influence of bit line coupling and twisting on the faulty behavior of DRAMs

Impact of stresses on the fault coverage of memory tests

Framework for fault analysis and test generation in drams

The effectiveness of Scan test and its new variants

The state-of-art future trends in testing embedded memories

Tests for address decoder delay faults in RAMs due to inter-gate opens

Soft faults and the importance of stresses in memory testing

Influence of bit line twisting on the faulty behavior or DRAMs

Detecting faults in peripheral circuits and an evaluation of SRAM tests

An industrial evaluation of DRAM tests
Journal article (2004) - AJ van de Goor (author)

Linked faults in random access memories: concept fault models, test algorithms, and industrial results

Effects of bit line coupling on the faulty behavior of DRAMs

Detecting intra-word faults in word-oriented memories