Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Conference paper (2019)

Authors

P. A. T Hart Student
M. Babaie Electronics - EEMCS
E. Charbon Intel Labs, Swiss Federal Institute of Technology
A. Vladimirescu University of California, ISEP, OLD QCD/Charbon Lab
F. Sebastiano (OLD)Applied Quantum Architectures
Research Group
Electronics (EEMCS) (TU Delft)
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Published Date

01-09-2019

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.

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