Calibration Techniques for Power-efficient Residue Amplifiers in Pipelined ADCs

Abstract

Residue amplification plays a key role in determining the energy efficiency, area and performance of high-speed pipelined ADCs. At its core, a residue amplifier simply consists of four transistors that transfer a differential input voltage to a capacitive load with the desired gain. However, in order to ensure gain accuracy over PVT, the core amplifier has to be augmented with extra circuitry to achieve high settling accuracy, at the expense of area and power dissipation. In this dissertation, techniques to improve the power efficiency of residue amplifiers were investigated, by adopting a two-pronged approach -

1. Developing new amplifier topologies which can achieve high resolution without relying on high DC-gain and settling accuracy, with the help of linearization in the analog domain, and

2. a deterministic calibration architecture which allows the calibration of linear gain error and distortion in background while achieving a fast convergence.