Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process

Conference paper (2014)

Authors

Vasiliki Giagka University College London
Nooshin Saeidi University College London
Andreas Demosthenous University College London
N. Donaldson University College London
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Published Date

01-01-2014

Language

English

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Abstract

We are developing an electrode array for epidural spinal cord stimulation and a thin integrated circuit (IC) is to be embedded in it. This paper focuses on the development and characterization of a manual process for thinning individual IC die and discusses the issues associated with thinning small dice by a manual process. The procedure allows easy and controlled post-separation thinning of small (about 1 mm2) silicon chips by grinding. A systematic approach was followed to characterize the technique and repeatability of the results. With the setup we introduced we were able to control the final thickness of the IC with a standard deviation of 9.2 μm. Although no chemical processing is used, a small grit size film can create smooth surfaces, with roughness comparable to reported values after etching, acting as the so-called 'stress-relief' step. Electrical tests performed on a thinned stimulator output stage IC indicated that no die damage was caused by the procedure. Some issues regarding the integration of thinned ICs on flexible substrates and the reliability of gold ball rivet bonds on the ICs' aluminium pads are also discussed.