A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

Journal article (2016)

Authors

M. Babaie Electronics - EEMCS
F Kuo Kuo Taiwan Semiconductor Manufacturing Company (TSMC)
H Chen Taiwan Semiconductor Manufacturing Company (TSMC)
L Cho Cho Taiwan Semiconductor Manufacturing Company (TSMC)
C. P. Jou Jou Taiwan Semiconductor Manufacturing Company (TSMC)
F. L. Hsueh Hsueh Taiwan Semiconductor Manufacturing Company (TSMC)
M. Shahmohammadi Electronics - EEMCS
R.B. Staszewski University College Dublin
Research Group
Electronics (EEMCS) (TU Delft)
Copyright: © 2016 M. Babaie, F Kuo, H Chen, L Cho, C. P. Jou, F. L. Hsueh, M. Shahmohammadi, R.B. Staszewski
DOI: https://doi.org/10.1109/JSSC.2016.2551738
Bluetooth Oscillators Internet of Things (IoT) Oscillators Low-power electronics Radio frequency CMOS integrated circuits Q-factor Digitally controlled oscillator Radiofrequency integrated circuits Switches Inductors CMOS digital integrated circuits MOSFET circuits Constant current sources Digital phase locked loops Radio transmitters Radiofrequency power amplifiers 1/f noise reduction Bluetooth low-energy mode CMOS transistors All-digital PLL Class-E-F2 switching power amplifier Direct DCO data modulation Efficiency 36 percent Energy-hungry RF circuits Fully integrated Bluetooth low-energy transmitter architecture Metal density Power 3.6 mW Power 5.5 mW Sampling rate reduction Size 28 nm Supply voltage reduction Switching current sources Threshold voltage Ultra-low power radios Radio transmitters All-digital PLL Bluetooth Low-Energy Class-E/F 2 power amplifier Low-power transmitter Low-voltage oscillator Switching current-source oscillator
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Published Date

2016

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

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