Neurons in Spiking Neural Networks (SNNs) communicate through spikes, similarly that neurons in the brain communicate, thus mimicking the brain. The working of SNNs is temporally based, as the spikes are time-dependent. SNNs have the benefit to perform continual classification, and are inherently more low-power than other Artificial Neural Networks (ANNs). Both the SNNs and other ANNs need to be trained to perform specific tasks. There are several types of methodologies to train SNNs, but there is yet no silver bullet. Backpropagation algorithms can train other ANNs, but SNNs cannot be trained using this algorithm since the spikes are not differentiable. Methods like Spike Timing Dependent Plasticity (STDP) or Liquid State Machine (LSM) have their limits. Where the complexity of SNNs depends on the dataset, the number of neurons, and other factors. There were currently no known SNN implementations for the given gesture, achieving near state-of-the-art results. The problem with the dataset is that usually no gesture is performed in front of the . The datasets contain noise, and some data samples belong to two or more classes simultaneously. The objective of this work is to develop an architecture and training methodology, that allows the classification of the dataset using SNNs. This work presents a novel, architectural training methodology Suino, which addresses the above problems. The architecture consists of two components: the first is the spatial classifier, and the second component is the temporal classifier. The frames from the dataset are filtered in the first stage, i.e. the spatial classifier. The output of the spatial classifier is the input for the temporal classifier, which deals with the temporal properties of the data. Suino does not provide false positives, that is the neurons do not spike on the input dataset if the input dataset does not belong to any of the trained classes; hence the method is robust. The training method is built around these components, existing of different classical training methods: backpropagation, clustering, or any other consisting of fixed threshold method for auto label correction. The second stage consists of a temporal classification method, trained using the Tempotron learning rule. The time-series dataset of gestures validated Suino. On the test set, the baseline method had an accuracy of 97.0% with 35K parameters, while the presented method had an accuracy of 90.87% with 21K parameters. Hence, the method is more robust against false detections and continuously performs classification.

One of the challenges of neuromorphic computing is efficiently routing spikes from neurons to their connected synapses. The aim of this thesis is to design a spike-routing architecture for flexible connections on single-chip neuromorphic systems. A model for estimating area, power consumption, memory, spike latency and link utilisation for neuromorphic spike-routing architecture is described. This model leads to the proposal for a new spike-routing architecture with a hybrid addressing scheme and a novel synaptic encoding scheme. The proposed architecture is implemented in a SystemC simulation tool with a supporting tool for encoding arbitrary SNN topologies for the synapse encoding scheme. Running the simulations with synthetic benchmarks and a handwriting recognition SNN shows that the proposed architecture is memory-efficient and provides low latency spike-routing with high synaptic activation concurrency.

As technology scaling enters the nanometer regime, device aging effects cause quality and reliability issues in CMOS Integrated Circuits (ICs), which in turn shorten its lifetime. Evaluating system aging through circuit simulations is very complex and time consuming. In this thesis, a framework is proposed, which allows for the evaluation of long-term aging effects of ICs and the corresponding measures to counteract premature failure. The focus of this work lies in the abstraction of low-level aging models to system-level models, in order to facilitate swift high-level simulation, without any knowledge of underlying circuit dynamics. Two major aging mechanisms, namely Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) degradation are considered for analysis. System-level aging management is performed with the prototype of a System-on-Chip (SoC) including a Management Unit (MU), which counteracts aging by employing Dynamic Voltage Scaling (DVS), Dynamic Frequency Scaling (DFS), and Adaptive Body Biasing (ABB). The simulation platform prototype is based on System-C AMS and a 65-nm technology library. This SoC simulation computes path delay using characterized models, which represent the aged behaviour of individual circuit elements. Results show that the obtained values are within 2% of circuit-level simulation values at the cost of a simulation time which is 15x lesser than conventional circuit simulators (e.g. Cadence NCSim).