Photovoltaic (PV) systems are often exposed to mismatch conditions caused by partial shading, different mounting angles, dust accumulation, cell degradation, etc. Among various techniques, PV to Virtual Bus Parallel Differential Power Processing (PV2VB P-DPP) has been proposed to overcome the mismatch among PV strings. This thesis focuses on the dynamic behavior of the PV2VB P-DPP configuration in order to analyze the system stability and design appropriate controllers. Configuration needs to control two different types of converters: 1- P-DPP converters (inner control loop) and 2- the Central Converter (outer control loop). Moreover, since the selection of capacitance for the virtual bus is a tradeoff between several factors, such as cost, stability, reliability, current ripple, and so on, this thesis provides a methodology to identify an acceptable range for the capacitance of the virtual bus.
This project used the state space representation to model the system owing to its simplicity and ability to provide a uniform and convenient starting point for linearization, stability evaluation, control design, and simulation. Since the system’s large signal model is nonlinear and difficult to work with, we linearized the state space equations (to achieve the small-signal model of a PV2VB P-DPP system consisting of any number of strings and converted them into the Laplace form to perform system analysis and controller design. Considering Gain and Phase Margin as the main design criteria, proportional control (Kp ) and integral control (Ki) were tuned for PI controllers using the SISO tool MATLAB toolbox for a PV system consisting of two PV strings. The system stability depends on two main aspects: the value of the virtual bus capacitor (CVB) and the voltage magnitude in the virtual bus (vV B ). The complete developed model has been implemented in MATLAB.
For the simulated PV2VB P-DPP system, a gain margin of 15.7 dB, a phase margin of 121 degrees, and a settling time of 0.8 s have been achieved for the outer control loop (central converter) by setting Ki and Kp to 5s^−1 and 0.5, respectively. On top of that, a gain margin of infinity dB, a phase margin of 91.2 degrees, and a settling time of 1 ms have been achieved for the inner control loop (DPP converter) by setting Ki and Kp to 10s^−1 and 0.1, respectively. Finally, it is shown that the virtual bus capacitor should be selected within the range 50µF- 5mF in order to make the system have higher stability margin. However, the final selected value of capacitance for the virtual bus is equal to 1.2 mF owing to other constraints, such as the expected ripple current.