Cardiovascular diseases are the leading cause of death in the devel- oped world. Preventing these deaths, require long term monitoring and manual inspection of ECG signals, which is a very time consum- ing process. Consequently, a wearable system that can automatically categorize beats is essential.
Neuromorphic machines have been introduced relatively recently in the science community. The aim of these machines is to emulate the brain. Their low power design makes them an optimal choice for a low power wearable ECG classifier.
As features are crucial in any machine learning system, this thesis aims at proposing an energy efficient feature extraction algorithm for ECG arrhythmia classification using neuromorphic machines. The feature extraction algorithm proposed in this thesis consists of the merger of a low power feature detection and a feature selection algorithm. Also, different network configurations have been investigated to achieve classification using an LSM architecture. The resulting system can accurately cluster seven beat types, has an overall classification rate of 95.5%, and consumes an estimate of 803.62 nW.

Neuromorphic engineering, aiming at emulating neuro-biological architectures in efficient ways, has been widely studied both on com- ponent and VLSI system level. The design space of neuromorphic neuron, the basic unit to conduct signal processing and transmission in nervous system, has been widely explored while that of synapse, the specialized functional unit connecting neurons, is less investigated.

In this thesis, a current-based phenomenological synapse model with power-efficient structures, consisting of efficient synaptic learn- ing algorithms and multi-compartment synapses, has been proposed. A vertical insight is given into the design space of spike-based learn- ing rules in regards to design complexity and biological fidelity. Due to various biological conducting mechanisms, the receptors, namely AMPA, NMDA and GABAa, demonstrate different kinetics in re- sponse to stimulus. The designed circuit offers distinctive features of receptors as well as the joint synaptic function. A better compu- tation ability is demonstrated through a cross-correlation detection experiment with a recurrent network of synapse clusters. The analog multi-compartment synapse structure is able to detect and amplify the temporal synchrony embedded in the synaptic noise. The maximum amplification level is 2 times larger than that of single-receptor con- figurations. The final design implemented in UMC65nm technology consumes 1.92, 3.36, 1.11 and 35.22pJ per spike event of energy for AMPA, NMDA, GABAa receptors and the advanced learning circuit, respectively.

The scalable simulation of neuron communication needs a large
amount of computing resources. The high throughput of data cause
the high requirement of interconnect network. This thesis is aimed
at the finding the efficient multi-FPGA connection for the neuron
network. First describe the characteristics of the network in terms
of the topology, routing and flow control. To find the efficient net-
work structure, analysis of the throughput for the different network
with different traffic pattern by considering the hopcount and band-
width are made. It shows that the multicast in mesh topology has
33% improvement comparing to unicast. Based on the interconnect
router architecture, a simulator is built to make a cycle accurate sim-
ulation in SystemC and test different traffic pattern by unicast and
multicast routing. To break the limitation of FPGA ports, the source
synchronous serdes connection is built by using the primitive in the
Xilinx FPGA. With the requirement of bandwidth, the possible solu-
tion of number of channels and the overhead are anaylsed.

As technology scaling enters the nanometer regime, device aging effects cause quality and reliability issues in CMOS Integrated Circuits (ICs), which in turn shorten its lifetime. Evaluating system aging through circuit simulations is very complex and time consuming. In this thesis, a framework is proposed, which allows for the evaluation of long-term aging effects of ICs and the corresponding measures to counteract premature failure. The focus of this work lies in the abstraction of low-level aging models to system-level models, in order to facilitate swift high-level simulation, without any knowledge of underlying circuit dynamics. Two major aging mechanisms, namely Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) degradation are considered for analysis. System-level aging management is performed with the prototype of a System-on-Chip (SoC) including a Management Unit (MU), which counteracts aging by employing Dynamic Voltage Scaling (DVS), Dynamic Frequency Scaling (DFS), and Adaptive Body Biasing (ABB). The simulation platform prototype is based on System-C AMS and a 65-nm technology library. This SoC simulation computes path delay using characterized models, which represent the aged behaviour of individual circuit elements. Results show that the obtained values are within 2% of circuit-level simulation values at the cost of a simulation time which is 15x lesser than conventional circuit simulators (e.g. Cadence NCSim).