Spiking neural networks (SNN), as the third-generation artificial neural network, has a similar potential pulse triggering mechanism to the biological neuron. This mechanism enables the spiking neural network to increase computing power compared to the traditional artificial neural network to process complex information. However, a large number of interconnection resources is required. This requirement is highly consistent with the characteristics of the network on chip (NoC). This thesis is aimed at developing a scalable cycle-accurate simulator based on Noxim, which provides a configurable NoC that can simulate neuron-to-neuron communication for delivering spiking traffic. This simulator achieves several configurable metrics including topology and routing schemes, network size, the number of channels, and neuron mapping methods. This thesis then evaluates the effects of these metrics on performance for two kinds of traffic patterns. To take power consumption and area into account, this thesis also provides an approximate estimate of area and power consumption for trade-offs in the early-design stage.

This dissertation describes an approach to building a self-timed asynchronous pulse-mode serial link circuit. Unlike asynchronous handshake circuits or synchronous circuits, this design style does not require any feedback control blocks, which can increase latency, or any clock recovery circuits, which can increase energy consumption and overhead. In addition, the serial link design strategy can reduce resource consumption and the complexity of wire and pins to facilitate placement and routing. In this dissertation, a self-timed asynchronous circuit is used, which necessitates the usage of the pulse logic family. The link also includes the two-wire burst mode protocol. The time notion is included in the zero-line and one-line of the link, and the timing information is included in the transmitted pulse signal without the use of a clock.

The overall design process follows a hierarchical structure. Firstly, to achieve the logic function, the link is designed at the behavior level with VHDL code. The serializer and deserializer functions should therefore be performed at the transistor level. They are based on the pulse-logic library, which should be built initially. The transistors utilized in the design are all HVT transistors, which reduce current leakage and power consumption. The final step is to do timing characterization and optimization to ensure that the design works properly under various conditions. The entire point-to-point link can be built by using 28nm technology and can function at 5Gb/s with a power consumption of 0.5mW.

Neuromorphic electronic systems have used asynchronous logic combined with continuous-time analog circuits to emulate neurons, synapses, and learning algorithms. It is attractive because of its low power consumption and feasible implementation. Typically, the neuron firing rates are lower than the modern digital systems. Thus, the endpoints of neuromorphic electronic systems are clusters of neurons instead of individual neurons. Address event representation (AER) was proposed in 1991 to multiplex communication for a cluster of neurons into an individual communication channel. AER circuits provide multiplexing/demultiplexing functionality for spikes that are asynchronously generated by/delivered to an array of individual neurons. Asynchronous techniques are not only used in neuromorphic electronic systems, but also widely used in globally asynchronous and locally synchronous (GALS) SoCs, or SoCs with full-asynchronous solutions. However, commercial tools on the market do not support designing asynchronous circuits, making the circuits cannot be adopted easily by most products. This thesis aims at addressing the challenge by providing an asynchronous library establishment strategy. The strategy uses SR-latches as standard asynchronous cells together with logic gates to build an AER communication circuit. With the strategy, the performance of using a modified traditional arbiter in the AER transmitter can be compared favourably with using state-of-the-art arbiters. A back-end flow and a verification flow are developed to evaluate the performance of the design as well as to check the feasibility of the strategy. The proposed 32-bit AER transmitter under TSMC 28nm CMOS technology sacrifices area and power to achieve better timing performance, where the modified arbiter inside has an 11.54% better response time than the arbiter who used to be the best in an old comparison.

Conversion from digital information to spike trains is needed for Spiking Neural Networks. Moreover, it is one of the most important steps for Spiking Neural Networks. This conversion could lead to much information loss depending on which encoding algorithm is used. Another major problem that can occur in a specific use-case is the limited bandwidth for the spikes that get generated through the encoding algorithm. In this thesis, we propose population Step Forward Encoding algorithm. This algorithm takes the signal encoding accuracy of Step Forward encoding algorithm and makes it into a population, generating multiple spike trains. This allows a higher threshold to encode a large part of the signal, increasing the efficiency. We show that population Step Forward Encoding algorithm doesn't just work good for the signal encoding accuracy, but also for the classification accuracy. Moreover, population Step Forward Encoding algorithm does not only have a high efficiency with a low spike count, it can also achieve higher efficiency with higher spike count. Thus, population Step Forward can make most use of a limited bandwidth of spikes.

Autonomous vehicle (AV technology) relies heavily on vision based applications like object recognition, obstacle/collision avoidance etc. In order to achieve this, understanding and estimating the dynamics in the environment is extremely important. LIDARs are proven to detect both shape as well as the speed/movement of the objects in the scene but one of the biggest challenges faced in adapting LIDAR technology is the huge amount of data it produces and the way it is processed. Most of this data is redundant static information which results in wastage of system memory, computational resources, power and time. Inspired from biological retina, first Neuromorphic-Retina for LIDAR is proposed that is able to extract and encode movement happening at particular distance, particular angle and with particular velocity from raw LIDAR temporal pulses into unique spike sequences so that the information about the dynamic environment can be efficiently classified and processed by event based and low powered Neuromorphic processing unit. The system is designed in such a way that it avoids consumption of large amount of computational resources and system memory. Simulation results show that the Retina is able to filter out redundant static information from the LIDAR data stream thereby reducing data throughput of around 50 - 70 % with 5 - 22 % spatial quality loss (based on scenario) as well as remove noise caused due to luminous reflections. This has tremendous impact on system latency and power consumption due to drop in memory accesses.