This paper evaluates the Single Event Upset (SEU) susceptibility of the NOEL-V processor, a novel and highly modular Intellectual Property (IP) Core by Cobham Gaisler on the Xilinx Kintex Ultrascale SRAM FPGA. The processor is based on the promising RISC-V architecture, an open s
...
This paper evaluates the Single Event Upset (SEU) susceptibility of the NOEL-V processor, a novel and highly modular Intellectual Property (IP) Core by Cobham Gaisler on the Xilinx Kintex Ultrascale SRAM FPGA. The processor is based on the promising RISC-V architecture, an open source Instruction Set Architecture (ISA) that is quickly rising in popularity. In order to characterize the performance of the NOEL-V IP Core in the space radiation environment, the KCU105 development board is used as Device Under Test (DUT) and irradiated with medium and high energy protons. Thanks to the NOEL-V configurability, several versions of the NOEL-V were tested and microarchitectural differences could be exposed. The biggest influence on user logic upsets is observed to be related to the use of an operating system. For a single-core, high-performance configuration, a foreseen in-orbit failure rate of one failure every 395 days is found for for a 51.6° circular orbit at 420 km altitude. Findings indicate that the NOEL-V processor, with the implementation of targeted fault tolerant measures, can be a viable choice for space missions even as soft-core in SRAM FPGA. Due to its modularity, the processor can be used for a multitude of mission types ranging from high performance general-purpose to low-end microcontroller applications. Error Detection And Correction, which is not available in open source versions, will be needed to protect user memory and make sure upsets in caches and Configuration RAM (CRAM) do not lead to a failure of the processor.
@en
