G

GS Garcea

11 records found

Trade-offs in buffer planning
Doctoral thesis (2005) - GS Garcea (author)

Throughput driven unidirectional bus design for NoC applications

Buffer planning for global wires under statistical process variations

Analytic model for area and power constrained optimal repeater insertion

Analytic model for area-constrained optimal repeater insertion

Simultaneous analytic area and power optimization for repeater insertion

Assessment of 3D interconnect geometry at the system level

Are wires plannable?
Conference paper (2001) - RHJM Otten (author), GS Garcea (author)

Derivation of dataflow networks for a domain specific applications
Conference paper (1999) - GS Garcea (author)

Modeling and determination of parasitics in submicron VLSI layouts

Derivation of a process network for the Jacobium processor
Conference paper (1999) - GS Garcea (author), B Kienhuis (author)