G

GS Garcea

11 records found

Authored

Trade-offs in buffer planning
Doctoral thesis (2005) - GS Garcea

Throughput driven unidirectional bus design for NoC applications
Conference paper (2004) - GS Garcea, N.P. van der Meijs

Analytic model for area-constrained optimal repeater insertion
Conference paper (2003) - GS Garcea, N.P. van der Meijs, RHJM Otten

Analytic model for area and power constrained optimal repeater insertion
Conference paper (2003) - GS Garcea, N.P. van der Meijs, RHJM Otten

Buffer planning for global wires under statistical process variations
Conference paper (2003) - GS Garcea, N.P. van der Meijs, RHJM Otten

Simultaneous analytic area and power optimization for repeater insertion
Conference paper (2003) - GS Garcea, N.P. van der Meijs, RHJM Otten

Are wires plannable?
Conference paper (2001) - RHJM Otten, GS Garcea

Assessment of 3D interconnect geometry at the system level
Conference paper (2001) - GS Garcea, N.P. van der Meijs

Derivation of a process network for the Jacobium processor
Conference paper (1999) - GS Garcea, B Kienhuis

Derivation of dataflow networks for a domain specific applications
Conference paper (1999) - GS Garcea

Modeling and determination of parasitics in submicron VLSI layouts