To improve the full-well capacity and linear dynamic range of CMOS image sensor, a special finger-shaped pinned photodiode (PPD) is designed. In terms of process, the first N-type ion implantation of the PPD N buried layer is extended under the transfer gate, thereby increasing the PPD capacitance. Based on TCAD simulation, the width and spacing of PPD were precisely adjusted. A high full-well capacity pixel design with a pixel size of 6 × 6 μm2 is realized based on the 0.18 μm CMOS process. The simulation results indicate that the pixel with the above structure and process has a depletion depth of 2.8 μm and a charge transfer efficiency of 100%. The measurement results of the test chip show that the full-well capacity can reach 68650e-. Compared with the conventional structure, the proposed PPD structure can effectively improve the full well capacity of the pixel.@en

To improve charge transfer efficiency (CTE) and eliminate image lag, the impact of spill back effect on image lag is studied in CMOS image sensors (CISs), particularly in high illumination condition. By establishing a mathematical model based on the thermionic emission and drift-diffusion theory, the physical mechanism of spill back effect is described. This model shows that a lower transfer gate (TG) operating voltage and a higher reset voltage of Floating Diffusion (FD) node would mitigate spill back effect. In a 0.18 μ m CMOS process, by setting that the gate voltage of transfer transistor and the reset voltage of FD is 2.8 V and 3.8 V respectively, CTE of the proposed pixel is increased to 100%. The theoretical analysis and TCAD simulation results can explain spill back effect and offer a reference for designing a high CTE pixel in high illumination CISs.

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