P

P Celinski

7 records found

Delay evaluation of high speed data-path circuits based on threshold logic

Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/Threshold-logic approach

State-of-the-art in CMOS threshold-logic VSLI gate implementations and applications

A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder

Area efficient, High speed parallel counter circuits using charge recycling threshold logic

Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates

Threshold logic parallel counters for 32-bit multipliers