AP

A.P. Pereira de Azevedo Filho

20 records found

Virtual execution platforms for mixed-time-criticality systems: The CompSOC architecture and design flow

Architecture and design flow for a debug event distribution interconnect

Scalable parallel programming applied to H.264/AVC decoding

An Instruction to Accelerate Software Caches

Efficient execution of video applications on heterogeneous multi- and many-core processors,
Doctoral thesis (2011) - A.P. Pereira de Azevedo Filho (author)

The SARC architecture

A multidimensional software cache for scratchpad-based systems

Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture

An efficient software cache for H.264 motion compensation

Scalar processing overhead on SIMD-only architectures

Scalability of macroblock-level parallelism for H.264 decoding

Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture

Parallel H.264 decoding on an embedded multicore processor

Analyzing scalability of deblocking filter of H.264 via TLP exploitation in a new many-core architecture

Analyses of video filtering on the cell processor

Parallel scalability of video decoders

Parallel Scalability of H.264

Exploiting parallelism of deblocking filter of H.264 on DTA architecture

Analysis of video filtering on the cell processor

H.264/AVC HDTV motion compensation soft IP