M

M Berekovic

10 records found

Authored

Architecture enhancements for the ADRES coarse-grained reconfigurable array
Journal article (2008) - F Bouwens, M Berekovic, B de Sutter, G. Gaydadjiev

Low power microarchitecture with instruction reuse
Conference paper (2008) - F Pratas, G. Gaydadjiev, M Berekovic, L Sousa, S Kaxiras

ADRES & DRESC: Architecture and compiler for coarse-grain reconfigurable processors
Book chapter (2007) - B Mei, M Berekovic, J-Y Mignolet

MT-adres: multithreading on coarse-grained reconfigurable architecture
Conference paper (2007) - K Wu, A Kanstein, J. Madsen, M Berekovic

Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.2624/AVC deblocking filter

Architectural Exploration of the ADRES coarse-grained reconfigurable array
Conference paper (2007) - F Bouwens, M Berekovic, A Kanstein, G. Gaydadjiev

Embedded Computer Systems: Architectures, Modeling, and Simulation

Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring

A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme
Conference paper (2006) - M Berekovic, T Niggemeier

Hardware and a tool chain for ADRES