Miniature ultrasound probes, such as intravascular ultrasound (IVUS) probes, are valuable diagnostic tools and provide image guidance during minimallyinvasive interventions. As more ultrasound transducer elements are built into such probes to improve image quality and frame rate, it becomes increasingly difficult to accommodate the cables needed to connect these elements to an imaging system. Among several reported cable-count reduction approaches, in-probe digitization of the received echo signals is a promising solution, as it allows digital data-link techniques to be leveraged to minimize cable count. This work takes a previously-developed application-specific integrated circuit (ASIC) for an IVUS probe as a starting point. This ASIC employs a load-modulation datalink to transmit digitized echo signals of one element via a single micro-coaxial cable at 0.6 Gb/s. This thesis extends this work to multi-bit per-symbol signalling to increase the data rate, allowing the echo signals of multiple elements to be combined into one cable. First, the measured performance of the existing ASIC is compared to simulation results, showing the need for an S-parameter based cable model to faithfully reproduce the measured performance. Based on this simulation model, load modulation with a maximum of three bits per symbol and a maximum symbol rate of 600 MHz is investigated. The trade-off between data-transmission conditions and bit-error rate is investigated and gives a general idea about how fast the data rate can be. An experimental setup is proposed to experimentally validate the performance of multi-bit load-modulation data links. For this, a prototype chip has been designed that includes a multi-bit load-modulation circuit and interfaces with an FPGA that provides test data. The chip has been taped out in a TSMC 0.18 um HV CMOS technology. Post-layout simulation shows that the prototype is able to generate a data rate of 1.6 Gb/s when there are two bits per symbol at the symbol rate of 800 MHz. Compared to the 0.6 Gb/s of the previous design, this is a substantially higher data rate.