In this work we present the pulsed current (PC) electrodeposition of Sn-Cu-Ni alloy as lead-free solder candidate, from choline chloride – ethylene glycol eutectic mixtures (1:2 molar ratio) onto copper metallic substrates. Electrolytes containing Sn²⁺, Cu²⁺ and Ni²⁺ salts in the selected deep eutectic solvent have been considered. The effect of the applied frequency of PC on the morphology, composition and melting point of the alloy is discussed and compared to the ones obtained using direct current (DC) plating mode. A refinement of the grain size and lower melting temperature of the alloy were noticed when pulsed current was applied. A comparative analysis of the electrochemical corrosion behaviour at macro- and micro- scale has been performed in 0.5 M and 0.1 M NaCl solutions involving potentiodynamic polarization curves, electrochemical impedance spectroscopy (EIS) and scanning vibrating electrode (SVET) techniques. Furthermore, an analysis after 96 h of exposure to salt mist test simulating a corrosive attack in harsh environment is presented, too. The obtained results showed enhanced corrosion resistance of the ternary alloys electrodeposited under PC conditions (the best for 1.67 Hz frequency) as compared to those using DC. Additionally, Raman spectroscopy evidenced the presence of tin oxi/hydroxy chloride and tin oxides as surface corrosion products. A corrosion mechanism has been proposed.

McCulloch-Pitts neuron structures are comprised of a number of synaptic inputs and a decision element, called soma. In this paper, we propose a 5-bit Graphene Nanoribbon (GNR)-based DAC to fulfill the role of the summation element featuring programmable input weights. The proposed GNR-based 5-bit DAC relies on: (i) GNR unit current cells and (ii) a GNR logic thermometric decoding block. Our implementation is based on mapping the GNR structure's conductance using Matlab and performing the required SPICE analysis using the Matlab based GNR Verilog-A model. The unit current cell geometry and bias conditions were chosen based on the unit cell's conductance map from which we derived its I ON/IOFF ratio, as well as transfer and output characteristics, resembling the classical MOSFET counterpart. By utilizing GNR devices instead of FinFET counterparts, a reduction of the active area of the 5-bit current DAC by up to a factor of three can be achieved. Furthermore, the GNR implementation achieved this while maintaining comparable INL and DNL performance to that of the FinFET variant, i.e., DNL of [-0.196, 0.088] LSB and INL of [-0.809, 0.364] LSB for the proposed GNR 5-bit DAC while operating at a supply voltage of only 0.2 V.