X-ray imaging systems play an important role in the diagnostic process of various medical conditions. Generating an accurate artificial X-ray image has multiple advantages. It allows for flexible configurations during generation. The resulting images can reduce testing time and cost, help the training of surgeons, and increase the amount of data for artificial intelligence model training. The generation of an X-ray image involves the simulation of a raytracing algorithm through a data model. In this research, a naive approach to this problem is examined. It was found that this approach can be improved by implementing model parallelization, data caching, and data compression. The resulting algorithm is simulated and validated in a software environment. This is then implemented for both an Ultrascale+ and a Versal FPGA. The results show that the algorithm can achieve real-time X-ray image generation, matching the performance of currently used detectors, provided that the required memory performance is achieved.

Current high-end medical X-ray intervention devices provide a tremendous amount of high-definition images per second. Combined with the additional inputs from the numerous auxiliary devices, processing and compositing the data in real-time quickly becomes an arduous engineering challenge. Furthermore, the critical nature of this application domain allows no room for error, whereas the process has to be simultaneously flexible enough to permit the unhindered work of the corresponding medical professional. Such medical imaging applications presently rely on complete hardware implementations of their processing pipelines and compositor engines, as opposed to earlier adopted paradigms of hardware-accelerated solutions. Said engines are usually realised in FPGA platforms due to their massively parallel computational capabilities and exceptional connectivity. However, given the vast amount of input streams arriving at the compositor's pipeline, switching and routing to available processing resources has remained a persistent issue. Present commercial solutions prove to be either too costly, too slow or too inflexible for developers to consider. On the other hand, academic literature centred around the subject is severely lacking. This thesis proposes a unique hardware architecture solution to mitigate the aforementioned problem. The proposed architecture, developed in collaboration with Philips Healthcare and TU Delft, exhibits an average end-to-end latency of 100 ns and a throughput of 7.2 Gb/s. Additionally, these results were realised under marginal resource utilisation, proving that such a switch can fit in the FPGA device and, subsequently, be developed as an integrated part of the compositor engine. Finally, the limited amount of reserved memory resources allowed for near-linear scalability of the proposed design should an increased amount of I/O devices be added; as well as dynamic portability should migration to smaller devices be a concern.