Today’s systems-on-chip (SOCs) and microprocessors are complex systems that require multiple temperature sensors to monitor temperature variations in multiple spots on a single silicon die. For such thermal management applications, specialized compact and fast temperature sensors are required. This is necessary because executing an intensive process on an SoC can cause local hotspots in a short amount of time, which can compromise reliability. Such temperature sensors should also be compatible with advanced nanometer CMOS technologies, since complex SoCs and microprocessors are typically implemented in aggressively scaled CMOS processes. @en

An array of temperature sensors based on the thermal diffusivity (TD) of bulk silicon has been realized in a standard 40-nm CMOS process. In each TD sensor, a highly digital voltage-controlled oscillator-based Σ Δ ADC digitizes the temperature-dependent phase shift of an electrothermal filter (ETF). A phase calibration scheme is used to cancel the ADC's phase offset. Two types of ETF were realized, one optimized for accuracy and one optimized for resolution. Sensors based on the accuracy-optimized ETF achieved a resolution of 0.36 °C (rms) at 1 kSa/s, and inaccuracies of ±1.4 °C (3 Σ , uncalibrated) and ±0.75 °C (3 Σ, room-temperature calibrated) from -40 °C to 125 °C. Sensors based on the resolution-optimized ETFs achieved an improved resolution of 0.21 °C (rms), and inaccuracies of ±2.3 °C (3 Σ, uncalibrated) and ±1.05 °C (3 Σ, room-temperature calibrated). The sensors draw 2.8 mA from supply voltages as low as 0.9 V, and occupy only 1650 μ m² , making them some of the smallest smart temperature sensors reported to date, and well suited for thermal monitoring applications in systems-on-chip.

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VCO-based phase-domain ΣΔ modulators employ the combination of a voltage-controlled-oscillator (VCO) and an up/down counter to replace the analog loop filter used in conventional ΣΔ modulators. Thanks to this highly digital architecture, they can be quite compact, and are expected to shrink even further with CMOS scaling. This paper describes the analysis and design of such converters. Trade-offs between design parameters and the impact of non-idealities, such as finite counter length and VCO non-linearity, are assessed through both theoretical analysis and behavioral simulations. The proposed design methodology is applied to the design of a phase-to-digital converter in a 40-nm CMOS process, which is used to digitize the output of a thermal-diffusivity temperature sensor, achieving ± 0.2° (3σ) phase inaccuracy from -40 to 125 °C and a sensor-limited resolution of 57 m° (RMS) within a 500-Hz bandwidth. Measurements on the prototype agree quite well with theoretical predictions, thus demonstrating the validity of the proposed design methodology.

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This work presents a thermal diffusivity (TD) sensor realized in nanometer (40nm) CMOS that demonstrates that the performance of such sensors continues to improve with scaling. Without trimming, the sensor achieves ±1.4°C (3σ) inaccuracy from -40 to 125°C, which is a 5× improvement over previous (non-TD) sensors intended for thermal monitoring. This improves to ±0.75°C (3σ) after a single-point trim, a level of accuracy that previously would have required two-point trimming. Furthermore, it operates from supply voltages as low as 0.9V, and occupies only 1650 μm2, making it one of the smallest smart temperature sensors reported to date. These advances are enabled by the use of a phase-calibration scheme and a highly digital phase-domain ΔΣ ADC.@en

Due to their relatively stable phase shift over temperature, electrothermal filters (ETFs) with an oxide heat path have been used as on-chip phase references, e.g. for thermal diffusivity (TD) temperature sensors. However, previous oxide ETFs were limited to SOI processes, whose deep-trench isolation could be used to create an oxide-dominated heat path. This paper describes, for the first time, an oxide ETF realized in a bulk CMOS process. It achieves a phase spread of 0.6 % (3 sigma, no trim) from -40 °C to 125 °C. When used as a reference for a TD temperature sensor, this translates into a temperature sensing spread of ±2.7 °C (3 sigma, no trim). This is 1.8 times less than the spread reported for SOI implementations, making the CMOS variant not only feasible, but also competitive.@en