In this contribution, We analyze the bandwidth versus accuracy trade-offs of conventional two-step de-embedding approaches, often employed to extract the device model parameters. The accuracy limitation of incorporating the pad/line section of classical DUT test-fixtures into shunt-series complex and frequency-dependent elements is analyzed by means of linear circuit simulations and EM parametric analysis. The de-embedding accuracy is then evaluated by employing 3D surfaces to include both the frequency and the geometrical dependency. To validate the presented analysis, classical device monitoring parameters are extracted versus frequency for the same nMOS device embedded in two different fixtures. One topology only supports pad level calibration, thus including the fixture pad/line section in the de-embedding process. The second topology allows a direct on-Wafer calibration (reference plane set on metal-1 in close proximity to the DUT) thus minimizing the residual parasitics to be removed by the de-embedding step. Experimental data are then presented and compared to simulation test benches to highlight the improved consistency of the extracted model parameters of the metal-1 calibration approach up to 220GHz.@en

In this contribution, we employ direct calibration/de-embedding approaches to validate the large signal device model of state-of-the-art HBTs and CMOS technologies operating in the mm-wave frequency band WR6. The capability of placing the first tier calibration reference plane in close proximity to the DUT allows the large signal metric to be directly compared with foundry models.@en