This letter proposes a new level-shifting structure that can convert extremely low levels of input voltages to high output voltages while maintaining excellent delay and power dissipation. In order to reduce contention and voltage swing in the internal nodes, the proposed circuit uses a diode-connected level shifter between gate terminals of the output inverter. Using a control circuit, only during the high-To-low transitions of the output, a current is forced into the diode-connected device. Measurement results demonstrate that the proposed circuit can consume as small energy as 4.2 fJ/transition with VDDL and VDDH of 0.35 V and 1.1 V, respectively, when implemented in a 40-nm CMOS technology. Furthermore, when fabricated in a 180-nm technology, the level-shifting circuit can convert VDDL as small as 80 mV to 1.8 V without using low-Threshold devices.

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This brief presents a fast and power-efficient voltage levelshifting circuit capable of converting extremely low levels of input voltages into high output voltage levels. The efficiency of the proposed circuit is due to the fact that not only the strength of the pull-up device is significantly reduced when the pull-down device is pulling down the output node, but the strength of the pull-down device is also increased using a low-power auxiliary circuit. Postlayout simulation results of the proposed circuit in a 0.18-μm technology demonstrate a total energy per transition of 157 fJ, a static power dissipation of 0.3 nW, and a propagation delay of 30 ns for input frequency of 1 MHz, low supply voltage level of VDDL = 0.4 V, and high supply voltage level of VDDH = 1.8 V.@en