A CMOS image sensor with a column-level multiple-ramp single-slope ADC

Snoeij, MF; Donegan, P; Theuwissen, A.J.P.A.M.; Makinwa, K.A.A.; Huijsing, J.H.

A CMOS image sensor with a column-level multiple-ramp single-slope ADC

Conference paper (2007)

Authors

MF Snoeij Electronic Instrumentation -

P Donegan External organisation

A.J.P.A.M. Theuwissen Electronic Instrumentation -

K.A.A. Makinwa Electronic Instrumentation -

J.H. Huijsing Electronic Instrumentation -

Research Group

Electronic Instrumentation () (TU Delft)

To reference this document use:

http://resolver.tudelft.nl/uuid:fbc90765-5960-4d50-9f8a-3cb2fbe4f1ff

More Info

expand_more

Published Date

2007

Language

Undefined/Unknown

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.