Detailed derivation and minimization of the equivalent parasitic capacitance of a high voltage multiplier based on the complete model

Wang, J.; de Haan, S.W.H.; Ferreira, J.A.

Detailed derivation and minimization of the equivalent parasitic capacitance of a high voltage multiplier based on the complete model

Conference paper (2013)

Authors

J. Wang Electrical Power Processing

S.W.H. de Haan Electrical Power Processing

J.A. Ferreira Electrical Power Processing

Research Group

Electrical Power Processing

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Published Date

2013

Language

English

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Research Group

Electrical Power Processing

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