Determined-Safe Faults Identification

A step towards ISO26262 hardware compliant designs

Conference paper (2020)

Authors

F. Augusto da Silva Cadence Design Systems, Computer Engineering - EEMCS
Ahmet Cagri Bagbaba Cadence Design Systems
Sandro Sartoni Politecnico di Torino
R. Cantoro Politecnico di Torino
Matteo Sonza Reorda Politecnico di Torino
S. Hamdioui Quantum & Computer Engineering
Christian Sauer Cadence Design Systems
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2020 F. Augusto da Silva, Ahmet Cagri Bagbaba, Sandro Sartoni, Riccardo Cantoro, Matteo Sonza Reorda, S. Hamdioui, Christian Sauer
DOI: https://doi.org/10.1109/ETS48528.2020.9131568
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Published Date

2020

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

The development of Integrated Circuits for the Automotive sector imposes on major challenges. ISO26262 compliance, as part of this process, entails complex analysis for the evaluation of potential random hardware faults. This paper proposes a systematic approach to identify faults that do not disrupt safety-critical functionalities and consequently can be considered Safe. By deploying code coverage and Formal verification techniques, our methodology enables the classification of faults that are unclassified by other technologies, improving ISO26262 compliance. Our results, in combination with Fault Simulation, achieved a Diagnostic Coverage of 93% in a CAN Controller. These figures allow an initial assessment for an ASIL B configuration of the IP.

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