Efficient Wafer Table Flatness Treatment via Smart Routing

Master thesis (2024)

Faculty

Electrical Engineering, Mathematics and Computer Science

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Published Date

26-08-2024

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

As a component of lithography machine, the wafer table plays an important role during wafer
exposure. The surface flatness condition of the WT will cause focus and overlay errors during
exposure and directly affect wafer distortion levels. This project takes advantage of global genetic algorithm to successfully develop a routing optimization design tool in MATLAB to deliver an efficient routing for genetic wafer fingerprints.

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Thesis_report_Jiawei_Li.pdf

File under embargo until 31-08-2026